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公开(公告)号：US5675526A
公开(公告)日：1997-10-07
申请号：US756708
申请日：1996-11-26
CPC分类号： G06F7/53 , G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/3885 , G06F2207/3828 , G06F7/49921
摘要： A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data multiply operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for multiplying a first packed data being stored at the first location with a second packed data being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.
摘要翻译： 处理器 处理器包括被耦合以接收控制信号的解码器。 控制信号具有第一源地址，第二源地址，目的地地址和操作字段。 第一个源地址对应于第一个位置。 第二源地址对应于第二位置。 目的地址对应于第三个位置。 操作字段指示要执行一种打包数据乘法运算。 处理器还包括耦合到解码器的电路。 该电路用于将在第一位置处存储的第一打包数据与存储在第二位置处的第二打包数据相乘。 电路还用于将相应的结果打包数据传送到第三位置。
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62.发明授权Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation 失效将相应的数据元素从两个源寄存器的一部分交换到处理器中的目标寄存器，以执行饱和公开(公告)号：US08521994B2
公开(公告)日：2013-08-27
申请号：US12975807
申请日：2010-12-22
IPC分类号： G06F9/315
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.
摘要翻译： 一种装置包括指令解码器，第一和第二源寄存器和耦合到解码器的电路，用于从源寄存器接收压缩数据，并响应于解码器接收到的包指令对压缩数据进行打包。 从第一源寄存器接收第一打包数据元素和第二打包数据元素。 从第二源寄存器接收第三打包数据元素和第四打包数据元素。 所述电路包装将每个打包数据元素的一部分包装到目的地寄存器中，其结果是来自与来自第一打包数据元素的部分相邻的第二打包数据元素的部分，以及来自与该部分相邻的第四打包数据元素的部分 从第三个打包的数据元素。
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公开(公告)号：US08495346B2
公开(公告)日：2013-07-23
申请号：US13444090
申请日：2012-04-11
IPC分类号： G06F9/315
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation.
摘要翻译： 处理器 处理器包括用于存储第一打包数据的第一寄存器，解码器和功能单元。 解码器具有控制信号输入。 控制信号输入用于接收第一控制信号和第二控制信号。 第一控制信号用于指示包装操作。 第二控制信号用于指示解封装操作。 功能单元耦合到解码器和寄存器。 功能单元用于使用第一打包数据执行包操作和拆包操作。 处理器还支持移动操作。
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公开(公告)号：US20130124830A1
公开(公告)日：2013-05-16
申请号：US13730841
申请日：2012-12-29
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
摘要翻译： 一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。
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公开(公告)号：US20130117547A1
公开(公告)日：2013-05-09
申请号：US13730837
申请日：2012-12-29
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
摘要翻译： 一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。
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公开(公告)号：US20110219214A1
公开(公告)日：2011-09-08
申请号：US13108723
申请日：2011-05-16
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation.
摘要翻译： 处理器 处理器包括用于存储第一打包数据的第一寄存器，解码器和功能单元。 解码器具有控制信号输入。 控制信号输入用于接收第一控制信号和第二控制信号。 第一控制信号用于指示包装操作。 第二控制信号用于指示解封装操作。 功能单元耦合到解码器和寄存器。 功能单元用于使用第一打包数据执行包操作和拆包操作。 处理器还支持移动操作。
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67.发明授权Method for packing a plurality of packed data elements in response to a pack instruction 失效响应于包指令来打包多个打包数据元素的方法
公开(公告)号：US5819101A
公开(公告)日：1998-10-06
申请号：US897283
申请日：1997-07-21
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30167 , G06F9/30181 , G06F7/49921
摘要： A method for manipulating packed data in a computer system. The method includes the steps of decoding a Single Instruction Multiple Data (SIMD) pack instruction. The instruction identifies a first and second packed data respectively including a first plurality of data elements and a second plurality of data elements. Each data element consists of a separate multiple bit data field, wherein each data element in the first plurality of data elements corresponds to a data element in the second plurality of data elements in a respective position. The method further includes the step of simultaneously copying, in response to the pack instruction, a part of each data element in the first plurality of data elements and a part of each corresponding data element in the second plurality of data elements into a third packed data as a plurality of separate result data elements.
摘要翻译： 一种在计算机系统中操纵打包数据的方法。 该方法包括对单指令多数据（SIMD）包指令进行解码的步骤。 该指令识别分别包括第一多个数据元素和第二多个数据元素的第一和第二打包数据。 每个数据元素由单独的多位数据字段组成，其中第一多个数据元素中的每个数据元素对应于相应位置的第二多个数据元素中的数据元素。 该方法还包括以下步骤：响应于包指令，将第一多个数据元素中的每个数据元素的一部分和第二多个数据元素中的每个相应数据元素的一部分同时复制成第三打包数据 作为多个单独的结果数据元素。
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68.发明授权Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register 失效执行具有元件大小控制位的指令，将源寄存器的半封装数据元素交错存储在相同大小的目标寄存器中公开(公告)号：US08601246B2
公开(公告)日：2013-12-03
申请号：US10185896
申请日：2002-06-27
IPC分类号： G06F15/80
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
摘要翻译： 一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。
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公开(公告)号：US20130124835A1
公开(公告)日：2013-05-16
申请号：US13730849
申请日：2012-12-29
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
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公开(公告)号：US20130124832A1
公开(公告)日：2013-05-16
申请号：US13730845
申请日：2012-12-29
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
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