公开(公告)号：US20180328989A1

公开(公告)日：2018-11-15

申请号：US16043468

申请日：2018-07-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3177 ,  G01R31/28 ,  G01R31/302

CPC classification number: G01R31/31713 ,  G01R31/2815 ,  G01R31/2851 ,  G01R31/2884 ,  G01R31/3025 ,  G01R31/31703 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318558

Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

公开(公告)号：US10054633B2

公开(公告)日：2018-08-21

申请号：US15467485

申请日：2017-03-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G01R31/28 ,  G01R31/302 ,  G01R31/3185 ,  G01R31/3177

CPC classification number: G01R31/31713 ,  G01R31/2815 ,  G01R31/2851 ,  G01R31/2884 ,  G01R31/3025 ,  G01R31/31703 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318558

Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

公开(公告)号：US20180224503A1

公开(公告)日：2018-08-09

申请号：US15945414

申请日：2018-04-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/31715 ,  G01R31/3172 ,  G01R31/31725 ,  G01R31/318547

Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

公开(公告)号：US10020032B2

公开(公告)日：2018-07-10

申请号：US15270673

申请日：2016-09-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G06F3/00 ,  G11C7/10 ,  G01R31/3185 ,  G06F13/40 ,  G06F13/42 ,  G06F3/06 ,  G06F13/38 ,  H04L29/08

CPC classification number: G11C7/1036 ,  G01R31/318572 ,  G06F3/0601 ,  G06F13/385 ,  G06F13/40 ,  G06F13/4022 ,  G06F13/4291 ,  G11C7/1066 ,  H04L29/08549 ,  H04L67/1097

Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

公开(公告)号：US10012695B2

公开(公告)日：2018-07-03

申请号：US15617446

申请日：2017-06-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3177 ,  G01R31/3183 ,  G01R31/28

CPC classification number: G01R31/31723 ,  G01R31/2896 ,  G01R31/31724 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/3183 ,  G01R31/318513 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318572 ,  G01R31/318594

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

公开(公告)号：US09964594B2

公开(公告)日：2018-05-08

申请号：US15442123

申请日：2017-02-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31713 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318508 ,  G01R31/318555

Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

公开(公告)号：US20180106861A1

公开(公告)日：2018-04-19

申请号：US15845235

申请日：2017-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/31724 ,  G01R31/31725 ,  G01R31/318536 ,  G01R31/318544

Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.

公开(公告)号：US20180038912A1

公开(公告)日：2018-02-08

申请号：US15783365

申请日：2017-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Vig

IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

公开(公告)号：US20180034465A1

公开(公告)日：2018-02-01

申请号：US15725948

申请日：2017-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: H03K19/0175 ,  H04L25/02

CPC classification number: H03K19/01759 ,  H04L25/0272

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

公开(公告)号：US20170322257A1

公开(公告)日：2017-11-09

申请号：US15657917

申请日：2017-07-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3185

CPC classification number: G01R31/318558 ,  G01R31/2851 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318572 ,  G01R31/318594

Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.