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    PACKAGE WITH STACKED POWER STAGE AND INTEGRATED CONTROL DIE
    63.
    发明申请
    PACKAGE WITH STACKED POWER STAGE AND INTEGRATED CONTROL DIE 有权

    公开(公告)号：US20210043551A1

    公开(公告)日：2021-02-11

    申请号：US16537517

    申请日：2019-08-09

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Woochan Kim ,  Vivek Kishorechand Arora ,  Benjamin Allen Samples

    IPC: H01L23/495 ,  H01L23/00 ,  H05K7/14 ,  H01L23/34

    Abstract: A package includes a semiconductor die forming a power field effect transistor (FET), a control die, and a first leadframe. The control die is arranged on a first surface of the first leadframe, and the semiconductor die is arranged on an opposing second surface of the first leadframe. The package further includes a second leadframe including a first surface and a second surface opposing the first surface, wherein the semiconductor die is arranged on the first surface of the second leadframe to facilitate heat transfer therethrough. The package also includes mold compound at least partially covering the semiconductor die, the control die, the first leadframe and the second leadframe with the second surface of the second leadframe exposed.

    EMBEDDED DIE PACKAGING WITH INTEGRATED CERAMIC SUBSTRATE
    65.
    发明申请
    EMBEDDED DIE PACKAGING WITH INTEGRATED CERAMIC SUBSTRATE 审中-公开

    公开(公告)号：US20200091076A1

    公开(公告)日：2020-03-19

    申请号：US16132906

    申请日：2018-09-17

    Applicant: Texas Instruments Incorporated

    Inventor： Woochan Kim ,  Mutsumi Masumoto ,  Kengo Aoya ,  Vivek Kishorechand Arora ,  Anindya Poddar

    IPC: H01L23/538 ,  H01L23/373 ,  H01L21/56 ,  H01L23/498

    Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

    Stress buffer layer in embedded package
    67.
    发明授权
    Stress buffer layer in embedded package 有权

    公开(公告)号：US10580715B2

    公开(公告)日：2020-03-03

    申请号：US16008119

    申请日：2018-06-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Woochan Kim ,  Masamitsu Matsuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar

    IPC: H01L23/10 ,  H01L23/34 ,  H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373

    Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

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