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    Embedded die packaging with integrated ceramic substrate
    1.
    发明授权
    Embedded die packaging with integrated ceramic substrate 有权

    公开(公告)号：US11183460B2

    公开(公告)日：2021-11-23

    申请号：US16132906

    申请日：2018-09-17

    Applicant: Texas Instruments Incorporated

    Inventor： Woochan Kim ,  Mutsumi Masumoto ,  Kengo Aoya ,  Vivek Kishorechand Arora ,  Anindya Poddar

    IPC: H01L23/538 ,  H01L23/373 ,  H01L21/56 ,  H01L23/498

    Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

    Fan-out electronic device
    3.
    发明授权
    Fan-out electronic device 有权

    公开(公告)号：US11410875B2

    公开(公告)日：2022-08-09

    申请号：US16225875

    申请日：2018-12-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Hau Thanh Nguyen ,  Woochan Kim ,  Yi Yan ,  Luu Thanh Nguyen ,  Ashok Prabhu ,  Anindya Poddar ,  Masamitsu Matsuura ,  Kengo Aoya ,  Mutsumi Masumoto

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00

    Abstract: An electronic device (100) includes a substrate (110) and an integrated circuit (120) provided on the substrate (110) having a surface facing away from the substrate (110). An insulating layer (150) extends over the substrate (110) and around the integrated circuit (120) to define an interface (154) between the insulating layer (150) and the integrated circuit (120). An electrically conductive via (130) is provided on the surface of the integrated circuit (120). An insulating material (140) extends over the via (130) and includes an opening (142) exposing a portion of the via (130). A repassivation member (162) extends over the insulating layer (150) and has a surface (164) aligned with the interface (154). An electrically conductive redistribution member (181) is electrically connected to the via (130) and extends over the repassivation member (162) into contact with the insulating layer (150).

    Stress buffer layer in embedded package
    4.
    发明授权
    Stress buffer layer in embedded package 有权

    公开(公告)号：US11183441B2

    公开(公告)日：2021-11-23

    申请号：US16808018

    申请日：2020-03-03

    Applicant: Texas Instruments Incorporated

    Inventor： Woochan Kim ,  Masamitsu Matsuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar

    IPC: H01L23/10 ,  H01L23/34 ,  H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373

    Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

    Stress Buffer Layer in Embedded Package
    5.
    发明申请
    Stress Buffer Layer in Embedded Package 审中-公开

    公开(公告)号：US20190385924A1

    公开(公告)日：2019-12-19

    申请号：US16008119

    申请日：2018-06-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Woochan Kim ,  Masamitsu Matsuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar

    IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00

    Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

    Thin Semiconductor Chip Mounting
    7.
    发明申请
    Thin Semiconductor Chip Mounting 审中-公开
    薄半导体芯片安装

    公开(公告)号：US20140069989A1

    公开(公告)日：2014-03-13

    申请号：US14024803

    申请日：2013-09-12

    Applicant: Texas Instruments Incorporated

    Inventor： Mutsumi Masumoto

    IPC: H01L21/50

    CPC classification number: H01L21/50 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13144 ,  H01L2224/75303 ,  H01L2224/75317 ,  H01L2224/75745 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2924/10253 ,  Y10T156/1168 ,  H01L2924/00 ,  H01L2924/00014

    Abstract: The embodiments of the invention provide a semiconductor chip mounting methods to prevent the occurrence of particles created while mounting a thin semiconductor chip onto a substrate. A semiconductor chip having conductive bumps on its main surface is held by its back via an elastic film using a suction tool having a plurality of suction holes, the semiconductor chip is positioned against a substrate provided with connection wires corresponding to said conductive bumps, and the semiconductor chip is mounted onto the substrate in such a manner that the conductive bumps connect to said connection wires, and uniform pressure is applied from the oversized bonding tool suction to the semiconductor chip via said film while said semiconductor chip is being pressed against said substrate by oversized bonding tool to keep constant pressure in order to bond said conductive bumps with said connection wires. The film assisted bonding tool has a film cooling system to assist in making vacuum holes and a through-hole tool movable relative to the bonding head to create a plurality of holes in said assist film with a plurality of needles.

    Abstract translation: 本发明的实施例提供一种半导体芯片安装方法，以防止在将薄半导体芯片安装到基板上时产生的颗粒的出现。 在其主表面上具有导电凸块的半导体芯片通过使用具有多个吸孔的抽吸工具通过弹性膜由其背面保持，半导体芯片位于与设置有与所述导电凸块相对应的连接线的基板上， 将半导体芯片以这样的方式安装到基板上，使得导电凸块连接到所述连接线，并且通过所述薄膜将超大的焊接工具抽吸均匀地施加到半导体芯片上，同时所述半导体芯片被所述衬底压靠在所述衬底上 超大的焊接工具以保持恒定的压力，以便将所述导电凸块与所述连接线接合。 薄膜辅助粘结工具具有薄膜冷却系统，以帮助制造真空孔，并且通孔工具相对于粘合头可移动，以在多个针中在所述辅助薄膜中产生多个孔。

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