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    MEMORY DEVICE AND METHOD FOR FORMING THEREOF
    61.
    发明申请
    MEMORY DEVICE AND METHOD FOR FORMING THEREOF 有权

    公开(公告)号：US20220037336A1

    公开(公告)日：2022-02-03

    申请号：US16941784

    申请日：2020-07-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chuan Yang

    IPC: H01L27/11 ,  H01L23/528 ,  H01L27/092

    Abstract: A semiconductor device includes a plurality of first memory cells in a memory region and a first cut-off transistor in a dummy region, the dummy region being adjacent to the memory region. Each of the plurality of the first memory cells includes a static random access memory (SRAM) cell. The static random access memory cell includes a first pull-down transistor and a second pull-down transistor. The plurality of the first memory cells includes a first memory cell. A first source/drain region of the first pull-down transistor in the first memory cell is electrically coupled to a first source/drain region of the first cut-off transistor and a second source/drain region of the first cut-off transistor is electrically coupled to a power supply voltage.

    Embedded SRAM write assist circuit
    62.
    发明授权
    Embedded SRAM write assist circuit 有权

    公开(公告)号：US11211116B2

    公开(公告)日：2021-12-28

    申请号：US16922270

    申请日：2020-07-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chuan Yang ,  Kian-Long Lim ,  Feng-Ming Chang

    IPC: G11C11/419 ,  G11C11/418

    Abstract: A static random-access memory (SRAM) semiconductor device including a memory unit is provided. The memory unit includes a bit array arranged in rows and columns. The columns are defined by a plurality of bit line pairs connecting to a plurality of memory cells in the column. The memory unit also includes an edge area adjacent an edge row of the bit array, wherein the edge row includes a plurality of dummy memory cells. The memory unit further includes a plurality of bit line drivers adjacent the bit array and opposite the edge area. The bit line drivers are for driving the bit lines with data to the memory cells during a write operation. The dummy memory cells include a write assist circuit for each bit line pair. The write assist circuit is used for facilitating the writing of the data on the bit line pairs to the memory cells.

    Embedded SRAM Write Assist Circuit
    65.
    发明申请
    Embedded SRAM Write Assist Circuit 有权

    公开(公告)号：US20210098058A1

    公开(公告)日：2021-04-01

    申请号：US16922270

    申请日：2020-07-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chuan Yang ,  Kian-Long Lim ,  Feng-Ming Chang

    IPC: G11C11/419 ,  G11C11/418

    Abstract: A static random-access memory (SRAM) semiconductor device including a memory unit is provided. The memory unit includes a bit array arranged in rows and columns. The columns are defined by a plurality of bit line pairs connecting to a plurality of memory cells in the column. The memory unit also includes an edge area adjacent an edge row of the bit array, wherein the edge row includes a plurality of dummy memory cells. The memory unit further includes a plurality of bit line drivers adjacent the bit array and opposite the edge area. The bit line drivers are for driving the bit lines with data to the memory cells during a write operation. The dummy memory cells include a write assist circuit for each bit line pair. The write assist circuit is used for facilitating the writing of the data on the bit line pairs to the memory cells.

    SOURCE/DRAIN FEATURE SEPARATION STRUCTURE
    67.
    发明申请
    SOURCE/DRAIN FEATURE SEPARATION STRUCTURE 有权

    公开(公告)号：US20250133716A1

    公开(公告)日：2025-04-24

    申请号：US18999095

    申请日：2024-12-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Chun Keng ,  Kuo-Hsiu Hsu ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Ping-Wei Wang

    IPC: H10B10/00 ,  H01L21/02 ,  H01L21/764 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85

    Abstract: A method according to the present disclosure includes receiving a structure. The structure includes a substrate, a first fin-shaped structure, a second fin-shaped structure, and a third fin-shaped structure disposed over the substrate, and a first isolation feature between the first fin-shaped structure and the second fin-shaped structure and a second isolation feature between the second fin-shaped structure and the third fin-shaped structure. The method further includes depositing a first dielectric layer over the first isolation feature and the second isolation feature, depositing a second dielectric layer over the first dielectric layer and the first isolation feature, but not over the second isolation feature, performing a first selective etching process to the first dielectric layer and the second dielectric layer, and performing a second selective etching process to the first dielectric layer over the second isolation feature. The second dielectric layer and the first dielectric layer have different etch resistance.

    Source/drain feature separation structure
    69.
    发明授权
    Source/drain feature separation structure 有权

    公开(公告)号：US12178032B2

    公开(公告)日：2024-12-24

    申请号：US17814279

    申请日：2022-07-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Chun Keng ,  Kuo-Hsiu Hsu ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Ping-Wei Wang

    IPC: H01L21/02 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B10/00

    Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

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