中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

18 records (took 0.02 seconds)

    Semiconductor memory structure
    2.
    发明授权
    Semiconductor memory structure 有权

    公开(公告)号：US11942169B2

    公开(公告)日：2024-03-26

    申请号：US17813891

    申请日：2022-07-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Wen Su ,  Kian-Long Lim ,  Wen-Chun Keng ,  Chang-Ta Yang ,  Shih-Hao Lin

    IPC: G11C17/18 ,  G11C7/18 ,  H10B20/00

    CPC classification number: G11C17/18 ,  G11C7/18 ,  H10B20/00

    Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.

    Fin-based well straps for improving memory macro performance
    3.
    发明授权
    Fin-based well straps for improving memory macro performance 有权

    公开(公告)号：US11937415B2

    公开(公告)日：2024-03-19

    申请号：US17874463

    申请日：2022-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chuan Yang ,  Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Wen-Chun Keng ,  Lien Jung Hung

    IPC: H10B10/00

    CPC classification number: H10B10/12 ,  H10B10/18

    Abstract: A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.

    Semiconductor memory structure
    4.
    发明授权
    Semiconductor memory structure 有权

    公开(公告)号：US11462282B2

    公开(公告)日：2022-10-04

    申请号：US16837227

    申请日：2020-04-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Wen Su ,  Kian-Long Lim ,  Wen-Chun Keng ,  Chang-Ta Yang ,  Shih-Hao Lin

    IPC: G11C17/18 ,  G11C7/18 ,  H01L27/112

    Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.

    SOURCE/DRAIN FEATURE SEPARATION STRUCTURE
    6.
    发明申请
    SOURCE/DRAIN FEATURE SEPARATION STRUCTURE 有权

    公开(公告)号：US20250133716A1

    公开(公告)日：2025-04-24

    申请号：US18999095

    申请日：2024-12-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Chun Keng ,  Kuo-Hsiu Hsu ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Ping-Wei Wang

    IPC: H10B10/00 ,  H01L21/02 ,  H01L21/764 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85

    Abstract: A method according to the present disclosure includes receiving a structure. The structure includes a substrate, a first fin-shaped structure, a second fin-shaped structure, and a third fin-shaped structure disposed over the substrate, and a first isolation feature between the first fin-shaped structure and the second fin-shaped structure and a second isolation feature between the second fin-shaped structure and the third fin-shaped structure. The method further includes depositing a first dielectric layer over the first isolation feature and the second isolation feature, depositing a second dielectric layer over the first dielectric layer and the first isolation feature, but not over the second isolation feature, performing a first selective etching process to the first dielectric layer and the second dielectric layer, and performing a second selective etching process to the first dielectric layer over the second isolation feature. The second dielectric layer and the first dielectric layer have different etch resistance.

    Source/drain feature separation structure
    7.
    发明授权
    Source/drain feature separation structure 有权

    公开(公告)号：US12178032B2

    公开(公告)日：2024-12-24

    申请号：US17814279

    申请日：2022-07-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Chun Keng ,  Kuo-Hsiu Hsu ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Ping-Wei Wang

    IPC: H01L21/02 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B10/00

    Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

    Integrated chip with improved latch-up immunity
    10.
    发明授权
    Integrated chip with improved latch-up immunity 有权

    公开(公告)号：US11257817B2

    公开(公告)日：2022-02-22

    申请号：US16808866

    申请日：2020-03-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang ,  Wen-Chun Keng ,  Chih-Chuan Yang ,  Shih-Hao Lin

    IPC: H01L27/092 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238

    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.

Patent Agency Ranking