公开(公告)号：US11527539B2

公开(公告)日：2022-12-13

申请号：US16888269

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Kian-Long Lim ,  Ping-Wei Wang ,  Lien Jung Hung ,  Ruey-Wen Chang

IPC: G11C7/12 ,  H01L27/11 ,  G11C8/08 ,  G11C11/412 ,  G11C11/417

Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, first and second pass-gate (PG) transistors, and bit line (BL) conductors. The first PU and the first PD transistors form a first inverter. The second PU and the second PD transistors form a second inverter. The first and the second inverters are cross-coupled to form two storage nodes that are coupled to the BL conductors through the first and the second PG transistors. The first and the second PU transistors are formed over an n-type active region over a frontside of the semiconductor structure. The first and the second PD transistors and the first and the second PG transistors are formed over a p-type active region over the frontside of the semiconductor structure. The BL conductors are disposed over a backside of the semiconductor structure.

公开(公告)号：US12048135B2

公开(公告)日：2024-07-23

申请号：US18064859

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Kian-Long Lim ,  Ping-Wei Wang ,  Lien Jung Hung ,  Ruey-Wen Chang

IPC: G11C5/06 ,  G11C7/12 ,  G11C8/08 ,  G11C11/412 ,  G11C11/417 ,  H10B10/00

CPC classification number: H10B10/12 ,  G11C7/12 ,  G11C8/08 ,  G11C11/412 ,  G11C11/417

Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, and first and second pass-gate (PG) transistors. A source, a drain, and a channel of the first PU transistor and a source, a drain, and a channel of the second PU transistor are collinear. A source, a drain, and a channel of the first PD transistor, a source, a drain, and a channel of the second PD transistor, a source, a drain, and a channel of the first PG transistor, and a source, a drain, and a channel of the second PG transistor are collinear.

公开(公告)号：US20210375883A1

公开(公告)日：2021-12-02

申请号：US16888269

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Kian-Long Lim ,  Ping-Wei Wang ,  Lien Jung Hung ,  Ruey-Wen Chang

IPC: H01L27/11 ,  G11C8/08 ,  G11C7/12

Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, first and second pass-gate (PG) transistors, and bit line (BL) conductors. The first PU and the first PD transistors form a first inverter. The second PU and the second PD transistors form a second inverter. The first and the second inverters are cross-coupled to form two storage nodes that are coupled to the BL conductors through the first and the second PG transistors. The first and the second PU transistors are formed over an n-type active region over a frontside of the semiconductor structure. The first and the second PD transistors and the first and the second PG transistors are formed over a p-type active region over the frontside of the semiconductor structure. The BL conductors are disposed over a backside of the semiconductor structure.

公开(公告)号：US20230267263A1

公开(公告)日：2023-08-24

申请号：US18308860

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ming Chang ,  Ruey-Wen Chang ,  Ping-Wei Wang ,  Sheng-Hsiung Wang ,  Chi-Yu Lu

IPC: G06F30/392 ,  H01L27/088 ,  G06F30/398 ,  H10B10/00

CPC classification number: G06F30/392 ,  H01L27/0886 ,  G06F30/398 ,  H10B10/12

Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.

公开(公告)号：US12160985B2

公开(公告)日：2024-12-03

申请号：US18151991

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Feng-Ming Chang ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Ruey-Wen Chang

IPC: G11C11/41 ,  G11C11/418 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B10/00

Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

公开(公告)号：US20240349474A1

公开(公告)日：2024-10-17

申请号：US18751938

申请日：2024-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Kian-Long Lim ,  Ping-Wei Wang ,  Lien Jung Hung ,  Ruey-Wen Chang

IPC: H10B10/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/412 ,  G11C11/417

CPC classification number: H10B10/12 ,  G11C7/12 ,  G11C8/08 ,  G11C11/412 ,  G11C11/417

Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, and first and second pass-gate (PG) transistors. A source, a drain, and a channel of the first PU transistor and a source, a drain, and a channel of the second PU transistor are collinear. A source, a drain, and a channel of the first PD transistor, a source, a drain, and a channel of the second PD transistor, a source, a drain, and a channel of the first PG transistor, and a source, a drain, and a channel of the second PG transistor are collinear.

公开(公告)号：US11552084B2

公开(公告)日：2023-01-10

申请号：US17248112

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Feng-Ming Chang ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Ruey-Wen Chang

IPC: H01L27/11 ,  G11C11/41 ,  H01L23/528 ,  H01L29/06 ,  G11C11/418 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

公开(公告)号：US20210305262A1

公开(公告)日：2021-09-30

申请号：US17248112

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Feng-Ming Chang ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Ruey-Wen Chang

IPC: H01L27/11 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  G11C11/418

Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

公开(公告)号：US20210124863A1

公开(公告)日：2021-04-29

申请号：US16796900

申请日：2020-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ruey-Wen Chang ,  Feng-Ming Chang

IPC: G06F30/392 ,  G06F30/3323

Abstract: A method of generating a layout for a semiconductor device includes the following step. A first layout having a first well region and second well regions is received. Mandrel blocking regions is defined in the first layout. First mandrels are generated outside of the mandrel blocking regions. Active structures are generated to overlap with the first mandrels in the second well region, and a width of the active structures in the second well region is adjusted. Second mandrels are generated in the first well region on two opposite sides of the first mandrels. Active structures are generated to overlap with the second mandrel in the first well region, and a width of the active structures in the first well region is adjusted. A second layout is generated based on the active structures located in the first well region and the second well regions.

公开(公告)号：US10977409B1

公开(公告)日：2021-04-13

申请号：US16796900

申请日：2020-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ruey-Wen Chang ,  Feng-Ming Chang

IPC: G06F30/3323 ,  G06F30/392 ,  H01L27/02 ,  H01L29/786 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092

Abstract: A method of generating a layout for a semiconductor device includes the following step. A first layout having a first well region and second well regions is received. Mandrel blocking regions is defined in the first layout. First mandrels are generated outside of the mandrel blocking regions. Active structures are generated to overlap with the first mandrels in the second well region, and a width of the active structures in the second well region is adjusted. Second mandrels are generated in the first well region on two opposite sides of the first mandrels. Active structures are generated to overlap with the second mandrel in the first well region, and a width of the active structures in the first well region is adjusted. A second layout is generated based on the active structures located in the first well region and the second well regions.