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61.发明授权System, method and computer program product for providing a programmable quiesce filtering register 失效用于提供可编程静态滤波寄存器的系统，方法和计算机程序产品公开(公告)号：US08140834B2
公开(公告)日：2012-03-20
申请号：US12037808
申请日：2008-02-26
CPC分类号： G06F9/4812
摘要： A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is identified. It is determined if the quiesce interruption request can be filtered by the processor. The determining is responsive to the filtering zone and to contents of a programmable filtering register for indicating exceptions to filtering performed by the receiving processor. The quiesce interruption request is filtered in response to determining that the request can be filtered.
摘要翻译： 一种用于提供可编程静态滤波寄存器的系统，方法和计算机程序产品。 该方法包括在处理器处接收静止中断请求。 处理器正在以一种模式执行。 识别与该模式相关联的过滤区域。 确定处理器是否可以过滤停顿中断请求。 该确定响应于过滤区域和可编程过滤寄存器的内容，用于指示接收处理器执行的过滤异常。 响应于确定可以对请求进行过滤，过滤掉静默中断请求。
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62.发明授权公开(公告)号：US08103851B2
公开(公告)日：2012-01-24
申请号：US11972697
申请日：2008-01-11
申请人： Dan F. Greiner , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
发明人： Dan F. Greiner , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
CPC分类号： G06F12/1009 , G06F12/1027
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.
摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 虚拟地址的索引部分用于引用转换表中的条目。 如果启用了转换表条目中包含的格式控制字段，则表项包含大小至少为1M字节的大块数据的帧地址。 然后将帧地址与虚拟地址的偏移部分组合以形成主存储器或存储器中的小4K字节数据块的转换地址。
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63.发明申请公开(公告)号：US20110320791A1
公开(公告)日：2011-12-29
申请号：US12821690
申请日：2010-06-23
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3017
摘要： A computing system method, program and hardware for correlation of millicode predictions with specific millicode routines receives architected millicode and stores the millicode in internal memory. The computer systems processors' pipeline is employed to predict and select a branch target buffer's (BTB) target address. A computer millicode control enabling an operating system (O/S) multi-task control between multiple user programs able to use millicode routines and ensuring that the programs do not interfere with each other, by use of a branch target buffer (BTB) prediction of a branch target to ensure that a millicode routine does not fetch outside of said millicode routine while performing operations as required by said millicode routing, said branch target buffer prediction employing a correlation mechanism for predicting millicoded branch millicode entry and millicode end instructions and for correlating millicode end predictions with specific millicode routines.
摘要翻译： 一个计算系统方法，程序和硬件相关的millicode预测与特定的millicode例程接收架构式的代码，并将millicode存储在内部存储器中。 计算机系统处理器的流水线用于预测和选择分支目标缓冲器（BTB）目标地址。 一种计算机微码控制，其使得能够使用毫秒代码程序的多个用户程序之间的操作系统（O / S）多任务控制，并且通过使用分支目标缓冲器（BTB）预测来确保程序不相互干扰 分支目标，以确保毫秒代码程序在执行所述毫代码路由所要求的操作之前不会从所述毫代码程序外部获取，所述分支目标缓冲器预测采用用于预测毫米编码的分支毫代数条目和毫分节结束指令的相关机制，并且用于关联millicode 用特定的millicode例程结束预测。
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公开(公告)号：US08019964B2
公开(公告)日：2011-09-13
申请号：US11972715
申请日：2008-01-11
申请人： Dan F. Greiner , Charles W. Gainey, Jr. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
发明人： Dan F. Greiner , Charles W. Gainey, Jr. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F12/16
CPC分类号： G06F12/1009 , G06F12/145 , G06F2212/651 , G06F2212/652
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of any one of a region first table, a region second table, a region third table, or a segment table are obtained. Based on the obtained initial origin address, a segment table entry is obtained which contains a format control and DAT protection fields. If the format control field is enabled, obtaining from the translation table entry a segment-frame absolute address of a large block of data in main storage. The segment-frame absolute address is combined with a page index portion and a byte index portion of the virtual address to form a translated address of the desired block of data. If the DAT protection field is not enabled, fetches and stores are permitted to the desired block of data addressed by the translated virtual address.
摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和区域第一表，区域秒表，区域第三表或段表中的任何一个的初始起始地址。 基于获得的初始起始地址，获得包含格式控制和DAT保护字段的段表条目。 如果格式控制字段被使能，则从转换表条目获得主存储器中的大块数据的段帧绝对地址。 分段帧绝对地址与虚拟地址的页索引部分和字节索引部分组合，以形成所需数据块的转换地址。 如果DAT保护字段未被使能，则获取和存储被允许被转换的虚拟地址寻址的所需数据块。
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65.发明申请METHOD FOR SERIALIZING TRANSLATION LOOKASIDE BUFFER ACCESS AROUND ADDRESS TRANSLATION PARAMETER MODIFICATION 有权串行翻译查询缓冲区访问方法地址转换参数修改方法公开(公告)号：US20090210650A1
公开(公告)日：2009-08-20
申请号：US12032178
申请日：2008-02-15
IPC分类号： G06F12/02
CPC分类号： G06F12/1027 , G06F2212/684
摘要： Embodiments of the invention include a method of synchronizing translation changes in a processor including a translation lookaside buffer, the method including setting a control bit to enable blocking of all fetch requests that miss the translation lookaside buffer without changing a translation state of the current process; if there is at least one pending translation, then waiting for completion of the at least one pending translation; and resetting the control bit. A processor and a computer program product are provided.
摘要翻译： 本发明的实施例包括一种在包括翻译后备缓冲器的处理器中同步翻译改变的方法，所述方法包括设置控制位以使得能够阻止错过所述翻译后备缓冲器的所有提取请求，而不改变当前进程的转换状态; 如果存在至少一个未完成的翻译，则等待完成至少一个等待翻译; 并重置控制位。 提供处理器和计算机程序产品。
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公开(公告)号：US20090182972A1
公开(公告)日：2009-07-16
申请号：US11972697
申请日：2008-01-11
申请人： DAN F. GREINER , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
发明人： DAN F. GREINER , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/1027
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.
摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 虚拟地址的索引部分用于引用转换表中的条目。 如果启用了转换表条目中包含的格式控制字段，则表项包含大小至少为1M字节的大块数据的帧地址。 然后将帧地址与虚拟地址的偏移部分组合以形成主存储器或存储器中的小4K字节数据块的转换地址。
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公开(公告)号：US20090182971A1
公开(公告)日：2009-07-16
申请号：US11972688
申请日：2008-01-11
申请人： DAN F. GREINER , Charles W. Gainey, JR. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
发明人： DAN F. GREINER , Charles W. Gainey, JR. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F9/30047 , G06F12/0215 , G06F12/1009 , G06F12/1036 , G06F12/145 , G06F2212/1052 , G06F2212/654 , G06F2212/656 , G06F2212/68
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being executed. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field.
摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，首先获得要被翻译的虚拟地址，并且获得翻译表层级的翻译表的初始起始地址。 基于获得的初始来源，获得段表条目。 段表项被配置为包含格式控制和访问有效性字段。 如果启用格式控制和访问有效性字段，则段表条目还包含访问控制字段，提取保护字段和段帧绝对地址。 仅当访问控制字段与程序状态字或正在执行的程序指令的操作数提供的程序访问键匹配时，才允许存储操作。 如果与虚拟地址相关联的程序访问密钥等于段访问控制字段，则允许获取操作。
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公开(公告)号：US5619715A
公开(公告)日：1997-04-08
申请号：US452638
申请日：1995-05-25
申请人： Robert M. Dinkjian , Lisa C. Heller , Steven R. Kordus , Kenneth A. Lauricella , Thomas W. Seigendall , Robert A. Skaggs , Nelson S. Xu
发明人： Robert M. Dinkjian , Lisa C. Heller , Steven R. Kordus , Kenneth A. Lauricella , Thomas W. Seigendall , Robert A. Skaggs , Nelson S. Xu
CPC分类号： G06F7/74 , G06F7/026 , G06F9/30018
摘要： A data processor processes data strings from memory where the data strings do not begin or end at a memory boundary. A string is defined in memory by a starting address, a byte count defining the total number of bytes in the string, and a byte offset defining the position of the first byte in the starting address location. The processor stores the byte count and decrements the byte count as each multi-byte word is processed. A byte count mask circuit generates a byte count mask which has all 1s for each byte count greater than the number of bytes per memory word. When the number of bytes remaining to be processed is below the number of bytes in a memory word, the byte count mask generates 1s only for the positions corresponding to the positions of bytes of the string in the last memory word. An offset register stores the offset defining the position of the first byte in the first memory word of the string. The offset is used to shift the byte count mask by a number of positions corresponding to the position of the first byte of the string and inserts 0s in the byte count mask for positions not belonging to the string. A byte-by-byte comparator determines string end conditions and provides an output word with a significant bit indication for each byte for which an end condition has been detected. The output of the byte-by-byte comparator is combined with the shifted byte count mask, and the result is decoded by means of a prioritized decoder which generates a string write mask.
摘要翻译： 数据处理器处理来自存储器的数据串，其中数据串不开始或在存储器边界处结束。 字符串在存储器中由起始地址定义，定义字符串总字节数的字节数以及定义起始地址位置中第一个字节的位置的字节偏移量。 处理器存储字节计数，并在处理每个多字节字时减少字节计数。 字节计数掩码电路产生一个字节计数掩码，每个字节计数的字节数大于每个存储字的字节数。 当待处理的剩余字节数低于存储器字中的字节数时，字节计数掩码仅针对与最后一个存储器字中字符串的字节位置相对应的位置产生1。 偏移寄存器存储定义字符串的第一个存储字中第一个字节的位置的偏移量。 偏移用于将字节计数掩码移位与字符串的第一个字节的位置相对应的位置数，并将不属于字符串的位置插入到字节计数掩码中的0。 逐字节比较器确定字符串结束条件，并为已经检测到结束条件的每个字节提供具有有效位指示的输出字。 逐字节比较器的输出与移位的字节计数掩码组合，结果通过生成字符串写掩码的优先级解码器进行解码。
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公开(公告)号：US5465374A
公开(公告)日：1995-11-07
申请号：US3369
申请日：1993-01-12
申请人： Robert M. Dinkjian , Lisa C. Heller , Steven R. Kordus , Kenneth A. Lauricella , Thomas W. Seigendall , Robert A. Skaggs , Nelson S. Xu
发明人： Robert M. Dinkjian , Lisa C. Heller , Steven R. Kordus , Kenneth A. Lauricella , Thomas W. Seigendall , Robert A. Skaggs , Nelson S. Xu
CPC分类号： G06F7/74 , G06F7/026 , G06F9/30018
摘要： A data processor processes data strings from memory where the data strings do not begin or end at a memory boundary. A string is defined in memory by a starting address, a byte count defining the total number of bytes in the string, and a byte offset defining the position of the first byte in the starting address location. The processor stores the byte count and decrements the byte count as each multi-byte word is processed. A byte count mask circuit generates a byte count mask which has all 1s for each byte count greater than the number of bytes per memory word. When the number of bytes remaining to be processed is below the number of bytes in a memory word, the byte count mask generates 1s only for the positions corresponding to the positions of bytes of the string in the last memory word. An offset register stores the offset defining the position of the first byte in the first memory word of the string. The offset is used to shift the byte count mask by a number of positions corresponding to the position of the first byte of the string and inserts 0s in the byte count mask for positions not belonging to the string. A byte-by-byte comparator determines string end conditions and provides an output word with a significant bit indication for each byte for which an end condition has been detected. The output of the byte-by-byte comparator is combined with the shifted byte count mask, and the result is decoded by means of a prioritized decoder which generates a string write mask.
摘要翻译： 数据处理器处理来自存储器的数据串，其中数据串不开始或在存储器边界处结束。 字符串在存储器中由起始地址定义，定义字符串总字节数的字节数以及定义起始地址位置中第一个字节的位置的字节偏移量。 处理器存储字节计数，并在处理每个多字节字时减少字节计数。 字节计数掩码电路产生一个字节计数掩码，每个字节计数的字节数大于每个存储字的字节数。 当待处理的剩余字节数低于存储器字中的字节数时，字节计数掩码仅针对与最后一个存储器字中字符串的字节位置相对应的位置产生1。 偏移寄存器存储定义字符串的第一个存储字中第一个字节的位置的偏移量。 偏移用于将字节计数掩码移位与字符串的第一个字节的位置相对应的位置数，并将不属于字符串的位置插入到字节计数掩码中的0。 逐字节比较器确定字符串结束条件，并为已经检测到结束条件的每个字节提供具有有效位指示的输出字。 逐字节比较器的输出与移位的字节计数掩码组合，结果通过生成字符串写入掩码的优先级解码器解码。
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公开(公告)号：US10521231B2
公开(公告)日：2019-12-31
申请号：US12822368
申请日：2010-06-24
摘要： In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.
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