公开(公告)号：US20200098659A1

公开(公告)日：2020-03-26

申请号：US16170067

申请日：2018-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/367 ,  H01L21/48

Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

公开(公告)号：US10460980B2

公开(公告)日：2019-10-29

申请号：US15888072

申请日：2018-02-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L21/762 ,  H01L21/761 ,  H01L21/311 ,  H01L21/763 ,  H01L21/764 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

Abstract: A method for fabricating semiconductor device comprising the steps of: forming a first trench and a second trench in a substrate; forming a liner in the first trench and the second trench; forming a first patterned mask on the substrate to cover the second trench; removing the liner in the first trench; removing the first patterned mask; and forming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench.

公开(公告)号：US20190206720A1

公开(公告)日：2019-07-04

申请号：US15888072

申请日：2018-02-04

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L21/762 ,  H01L21/764 ,  H01L21/311 ,  H01L21/763 ,  H01L21/761

Abstract: A method for fabricating semiconductor device comprising the steps of: forming a first trench and a second trench in a substrate; forming a liner in the first trench and the second trench; forming a first patterned mask on the substrate to cover the second trench; removing the liner in the first trench; removing the first patterned mask; and forming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench.

公开(公告)号：US09048285B2

公开(公告)日：2015-06-02

申请号：US13932009

申请日：2013-07-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tong-Yu Chen ,  Kuo-Yuh Yang

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3081 ,  H01L21/76232 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76898 ,  H01L29/0649

Abstract: A semiconductor structure includes a SOI/BOX semiconductor substrate, a device, a deep trench, a silicon layer, and a dielectric layer. The deep trench is adjacent to the device and extends through a shallow trench isolation layer within the SOI layer and the BOX layer and into the base semiconductor substrate. The silicon layer is disposed within a lower portion of the deep trench. The silicon layer has a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate. The dielectric layer is disposed within the deep trench and on the silicon layer. The deep trench can be formed before or after formation of an interlayer dielectric.

Abstract translation: 半导体结构包括SOI / BOX半导体衬底，器件，深沟槽，硅层和电介质层。 深沟槽与器件相邻，并延伸穿过SOI层和BOX层内的浅沟槽隔离层并进入基底半导体衬底。 硅层设置在深沟槽的下部内。 硅层具有与基底半导体衬底的顶表面高度基本相同或更低的顶表面高度。 电介质层设置在深沟槽内和硅层上。 深沟槽可以在形成层间电介质之前或之后形成。