公开(公告)号：US5940392A

公开(公告)日：1999-08-17

申请号：US366809

申请日：1994-12-30

Applicant: William Lo ,  Ian Crayford

Inventor： William Lo ,  Ian Crayford

IPC: H04L12/18 ,  H04L12/44 ,  H04L12/46 ,  H04L29/06 ,  H04J3/26 ,  H04J3/36

CPC classification number: H04L12/46 ,  H04L45/7453 ,  H04L63/10 ,  H04L12/18 ,  H04L12/44

Abstract: In a repeater having multiple ports and receiving at a source port a data packet containing a received address, an address mapping system including a content addressable memory (CAM) with address registers containing stored addresses, and an address mapping matrix coupled to said CAM, for perfectly mapping any of the address registers to any of the ports. According to one aspect of the invention, it operates in a repeater having an address compare and disrupt security system. The preferred embodiment of the present invention includes a content addressable memory having address registers containing stored individual and multicast addresses associated with each repeater port, and an address mapping matrix including a disrupt enable circuit associated with each port, for enabling the disruption of the data packet at that port when the received destination address does not match the associated stored addresses, and for disabling the disruption of the data packet at that port when the received destination address matches the stored address in a particular register and that particular register is mapped to that port via an address mapping register.

Abstract translation: 在具有多个端口并且在源端口处接收包含接收到的地址的数据分组的中继器中，包括具有包含存储的地址的地址寄存器的内容可寻址存储器（CAM）的地址映射系统和耦合到所述CAM的地址映射矩阵， 将任何地址寄存器完美地映射到任何端口。 根据本发明的一个方面，其操作在具有地址比较和中断安全系统的中继器中。 本发明的优选实施例包括内容可寻址存储器，其具有包含与每个中继器端口相关联的存储的单独和多播地址的地址寄存器，以及包括与每个端口相关联的中断使能电路的地址映射矩阵，以便能够中断数据分组 当接收到的目的地地址与相关联的存储地址不匹配时，在该端口处，并且当接收到的目的地地址与特定寄存器中存储的地址匹配并且该特定寄存器被映射到该端口时禁止在该端口处的数据分组的中断 通过地址映射寄存器。

公开(公告)号：US5850515A

公开(公告)日：1998-12-15

申请号：US827675

申请日：1997-04-10

Applicant: William Lo ,  Ian S. Crayford

Inventor： William Lo ,  Ian S. Crayford

IPC: H04L29/06 ,  G06F13/00

CPC classification number: H04L63/123 ,  H04L29/06 ,  H04L63/1416 ,  H04L63/1441

Abstract: A method and apparatus for securing a network from access by unauthorized end stations. A port in a multiport repeater can be disabled automatically upon detection of an unknown source address in a data packet. In addition, an interrupt signal is provided to the indicate the detection of an intruder. Further, the disabling of the port can be done substantially immediately to interrupt the re-transmission of a single packet. Alternatively, the disabling of a port can be done programmably after a predetermined number of intruder packets have been detected, or after the verification of packet integrity.

Abstract translation: 一种用于保护网络免受未经授权的终端站访问的方法和装置。 检测到数据包中的未知源地址时，可以自动禁用多端口转发器中的端口。 另外，提供中断信号以指示入侵者的检测。 此外，端口的禁用可以基本上立即进行以中断单个分组的重传。 或者，在已经检测到预定数量的入侵者分组之后，或者在验证分组完整性之后，可以可编程地完成端口的禁用。

公开(公告)号：US5590201A

公开(公告)日：1996-12-31

申请号：US337634

申请日：1994-11-10

Applicant: William Lo

Inventor： William Lo

IPC: H04L12/44 ,  H04L12/46 ,  H04L9/00

CPC classification number: H04L12/44 ,  H04L45/7453 ,  H04L12/46 ,  Y10S370/911

Abstract: In a managed repeater having an address learn capability wherein receipt at a particular port of a data packet having a received source address different from a stored source address associated with the particular port replaces the stored source address with the received source address, a source address locking circuit includes an address learn circuit associated with the particular port, for replacing the stored source address with the received source address when the stored source address does not match the received source address, and an address lock register for the particular port, coupled to the address learn circuit, for storing a bit value to disable the address learn circuit from replacing the stored source address with the received source address. This managed repeater provides improved security in a network having source address updating by allowing an administrator to disable the source address update for a particular port in the managed repeater. Each address lock register is externally programmable, and the administrator is able to program time windows to disable source address updating for a particular port. The administrator may program each address lock register independently to prevent the stored source address associated with each port from being updated. The managed repeater allows the administrator to determine on a per port basis whether the managed repeater's address learning capability should be enabled or disabled for a programmable time window.

Abstract translation: 在具有地址学习功能的托管中继器中，其中在具有与存储的与特定端口相关联的源地址不同的接收源地址的数据分组的特定端口处的接收将所存储的源地址替换为接收到的源地址，源地址锁定 电路包括与特定端口相关联的地址学习电路，用于在存储的源地址与接收到的源地址不匹配时替换存储的源地址和用于特定端口的地址锁定寄存器，耦合到该地址 学习电路，用于存储位值，以禁止地址学习电路用接收到的源地址替换存储的源地址。 该托管中继器通过允许管理员禁用托管中继器中的特定端口的源地址更新来提供具有源地址更新的网络中的改进的安全性。 每个地址锁定寄存器是外部可编程的，管理员能够编程时间窗口来禁用特定端口的源地址更新。 管理员可以独立编程每个地址锁定寄存器，以防止与每个端口相关联的存储的源地址被更新。 托管中继器允许管理员在每个端口基础上确定在可编程时间窗口中是否启用或禁用托管中继器的地址学习能力。

公开(公告)号：US5550803A

公开(公告)日：1996-08-27

申请号：US406085

申请日：1995-03-17

Applicant: Ian S. Crayford ,  William Lo

Inventor： Ian S. Crayford ,  William Lo

IPC: H04L12/26 ,  H04L12/44 ,  H04J3/14

CPC classification number: H04L43/00 ,  H04L12/2602 ,  H04L12/44 ,  H04L43/0847 ,  H04Q2213/13172 ,  H04Q2213/13293 ,  H04Q2213/13396

Abstract: A method and system for providing statistical network information carried in a data packet being transmitted on a network. The method includes the steps of receiving a data packet having a data portion on a repeater and transferring the data portion to a management unit. The method further includes the step of appending statistical information to the data portion during an inter-packet gap period. The apparatus for providing statistical information in a data packet on a network includes a repeater mechanism, a management unit mechanism, and a packet tagging circuit. The repeater mechanism receives a data packet having a data portion, the management unit mechanism determines statistical information based on the data packet, and the packet tagging circuit appends information to the data portion of the data packet during an inter-packet gap period.

Abstract translation: 一种在网络上发送的数据包中提供统计网络信息的方法和系统。 该方法包括以下步骤：在中继器上接收具有数据部分的数据分组，并将数据部分传送到管理单元。 该方法还包括在数据包间隔时段期间将统计信息附加到数据部分的步骤。 用于在网络上的数据分组中提供统计信息的装置包括中继器机制，管理单元机制和分组标签电路。 中继器机构接收具有数据部分的数据分组，管理单元机构基于数据分组确定统计信息，并且分组标签电路在分组间间隔时段期间将信息附加到数据分组的数据部分。

公开(公告)号：US5353353A

公开(公告)日：1994-10-04

申请号：US53797

申请日：1993-04-26

Applicant: Nader Vijeh ,  William Lo

Inventor： Nader Vijeh ,  William Lo

IPC: H04L29/08 ,  H04L12/22 ,  H04L12/44 ,  H04L29/06 ,  H04K1/00

CPC classification number: H04L63/0227 ,  H04L12/22 ,  H04L12/44

Abstract: A system is provided for use in a network providing security to ensure the prevention of unauthorized receipt of data. The system utilizes a jamming sequence to prevent unauthorized ports from receiving certain data. Repeaters utilized in the network are provided with the capability to detect a particular data sequence to provide the improved features.

Abstract translation: 提供一种用于提供安全性的网络中的系统，以确保防止未经授权的数据接收。 系统利用干扰序列来防止未经授权的端口接收某些数据。 在网络中使用的中继器具有检测特定数据序列以提供改进的特征的能力。

公开(公告)号：US08718079B1

公开(公告)日：2014-05-06

申请号：US13155085

申请日：2011-06-07

Applicant: William Lo ,  Sehat Sutardja

Inventor： William Lo ,  Sehat Sutardja

IPC: H04L12/28 ,  H04L12/56 ,  H04J3/16 ,  H04J3/22 ,  H04J3/04

CPC classification number: H04L49/557 ,  H04L49/30

Abstract: A first integrated circuit (IC) includes a first set of M serializer/deserializer (SERDES) modules configured to communicate with a first set of M SERDES modules of a switch IC of a switch, respectively, where M is an integer greater than 1. The first IC includes a first set of N SERDES modules configured to communicate with a first set of N ports of the switch, respectively, where N=(M−1). The first IC includes a first set of N multiplexer modules configured to communicate with (i) the N SERDES modules in the first set of N SERDES modules, respectively, and (ii) the M SERDES modules in the first set of M SERDES modules of the first IC. Each of the N multiplexer modules is configured to communicate with a pair of SERDES modules in the first set of M SERDES modules of the first IC.

Abstract translation: 第一集成电路（IC）包括第一组M串行器/解串器（SERDES）模块，其被配置为分别与开关的开关IC的第一组M SERDES模块通信，其中M是大于1的整数。 第一IC包括第一组N SERDES模块，其被配置为分别与开关的N个端口的第一组通信，其中N =（M-1）。 第一IC包括第一组N个多路复用器模块，其被配置为分别与（i）第一组N个SERDES模块中的N个SERDES模块进行通信，以及（ii）第一组M SERDES模块中的M个SERDES模块 第一个IC。 N个多路复用器模块中的每一个被配置为与第一IC的第一组M SERDES模块中的一对SERDES模块通信。

公开(公告)号：US08320400B1

公开(公告)日：2012-11-27

申请号：US12836226

申请日：2010-07-14

Applicant: William Lo

Inventor： William Lo

IPC: H04L12/66 ,  H04L12/50 ,  H04L12/28 ,  H04L12/56 ,  H04Q11/00

CPC classification number: H04L12/413

Abstract: A system including a first module configured to receive first data at an adaptable rate over a first electrical interface. The system further includes a nibble replicator module configured to generate second data in response to the first data by selectively expanding each nibble of the first data into a byte of the second data. The system also includes a repeater module configured to generate third data in response to the second data by selectively outputting each block of the second data multiple times in the third data. The system further includes a delimiter injection module configured to generate output data on a plurality of lanes in response to the third data by outputting delimiter symbols on a predetermined one of the plurality of lanes. The system also includes a second module configured to transmit the output data at a predetermined cumulative rate over a second electrical interface.

Abstract translation: 一种系统，包括：第一模块，被配置为以适应速率在第一电接口上接收第一数据。 该系统还包括一个半字节复制器模块，配置为通过选择性地将第一数据的每个半字节扩展成第二数据的字节来响应于第一数据生成第二数据。 该系统还包括中继器模块，该中继器模块经配置以通过在第三数据中选择性地输出第二数据的多个块来产生响应于第二数据的第三数据。 所述系统还包括定界器注入模块，所述分隔符注入模块被配置为通过在所述多个通道中的预定的一个通道上输出定界符号来响应于所述第三数据而在多个通道上产生输出数据。 该系统还包括第二模块，其被配置为通过第二电接口以预定的累积速率发送输出数据。

公开(公告)号：US08286017B2

公开(公告)日：2012-10-09

申请号：US13099947

申请日：2011-05-03

Applicant: William Lo

Inventor： William Lo

IPC: G06F1/00

CPC classification number: H04L12/12 ,  Y02D50/20 ,  Y02D50/40 ,  Y02D50/42

Abstract: A network interface including: a medium access control device configured to operate at a first power state during an inactive power mode, and operate at a second power state during an active power mode; a physical layer device including (i) an energy detect module configured to detect energy on a medium during the inactive power mode, and (ii) an energy save module configured to time a first pre-determined period subsequent to the energy detect module detecting energy on the medium. The medium access control device is further configured to, subsequent to the energy detect module detecting energy on the medium, transition to the second power state of the active power mode, and communication with the medium access control device via the medium is enabled subsequent to expiration of the first pre-determined period.

Abstract translation: 一种网络接口，包括：媒体接入控制装置，被配置为在无功功率模式期间在第一功率状态下操作，并且在有功功率模式期间在第二功率状态下操作; 物理层设备，包括：（i）能量检测模块，其被配置为在所述非活动功率模式期间检测介质上的能量;以及（ii）能量保存模块，其被配置为在所述能量检测模块检测能量之后的第一预定时段 在媒体上 介质访问控制装置还被配置为在能量检测模块检测介质上的能量之后，转换到有功功率模式的第二功率状态，并且在到期后能够经由介质与介质访问控制装置进行通信 的第一个预定时期。

公开(公告)号：US08144635B1

公开(公告)日：2012-03-27

申请号：US13185133

申请日：2011-07-18

Applicant: William Lo

Inventor： William Lo

IPC: H04B3/36 ,  H04L12/28 ,  H04J3/16 ,  G06F15/16

CPC classification number: H04L49/40 ,  H04L49/30 ,  H04L49/351

Abstract: A first device comprising: a pin interface having a plurality of pins; a data signal transmitter configured to respectively transmit, to a second device, a first plurality of data signals over a first set of pins of the plurality of pins of the pin interface; an encoder configured to generate a first encoded control signal based on having encoded a first plurality of control signals; and a control signal transmitter configured to transmit, to the second device, the first encoded control signal over a first pin of the plurality of pins of the pin interface, wherein the first pin is not of the first set of pins.

Abstract translation: 一种第一装置，包括：具有多个销的销接口; 数据信号发送器，被配置为分别在所述引脚接口的所述多个引脚的第一组引脚上向第二设备发送第一多个数据信号; 编码器，被配置为基于编码了第一多个控制信号来产生第一编码控制信号; 以及控制信号发射器，被配置为在所述引脚接口的所述多个引脚的第一引脚上向所述第二设备传输所述第一编码控制信号，其中所述第一引脚不是所述第一组引脚。

公开(公告)号：US08094668B1

公开(公告)日：2012-01-10

申请号：US12714746

申请日：2010-03-01

Applicant: William Lo ,  Nafea Bishara

Inventor： William Lo ,  Nafea Bishara

IPC: H04L12/28

CPC classification number: G06F13/385 ,  H04J3/0697

Abstract: A physical layer device includes a serial media independent interface (SMII). The SMII includes a first terminal configured to receive a first data stream. The first data stream is received at the first terminal in accordance with a first frequency. The SMII further includes a transmit circuit configured to (i) sample, on a rising edge of a clock, the first data stream received at the first terminal to generate a second data stream to be transmitted from the physical layer device, and (ii) sample, on a falling edge of the clock, the first data stream received at the first terminal to generate a third data stream to be transmitted from the physical layer device. Each of the second data stream and the third data stream has a second frequency, and the first frequency is twice the second frequency.

Abstract translation: 物理层设备包括与串行媒体无关的接口（SMII）。 SMII包括被配置为接收第一数据流的第一终端。 第一数据流根据第一频率在第一终端处被接收。 SMII还包括发射电路，其被配置为（i）在时钟的上升沿采样在第一终端处接收的第一数据流，以产生要从物理层设备传输的第二数据流，以及（ii） 在时钟的下降沿采样在第一终端处接收的第一数据流，以产生要从物理层设备发送的第三数据流。 第二数据流和第三数据流中的每一个具有第二频率，第一频率是第二频率的两倍。