公开(公告)号：US4146481A

公开(公告)日：1979-03-27

申请号：US803983

申请日：1977-06-06

申请人： Susumu Nagatoshi ,  Yoshiharu Kato

发明人： Susumu Nagatoshi ,  Yoshiharu Kato

IPC分类号： B01D29/46 ,  B01D33/06 ,  B01D33/073 ,  E03D5/016 ,  B01D29/42

CPC分类号： B01D33/073 ,  B01D2201/282 ,  B01D2201/287 ,  B01D29/46

摘要： Disclosed herein is an improvement in a filter of the type having a plurality of filtering plates vertically spaced at fixed intervals to interpose filtering spaces therebetween and as many scrapers laid outwardly from the axis of the stack of filtering plates and inserted one each into the filtering spaces, i.e. between the adjacent filtering plates, the improvement which includes giving each filtering plate a perfectly circular periphery so as to avoid formation of any protuberance from the circumferences and, at the same time, disposing the scrapers so as to keep sliding contact with the adjacent filtering plates.

摘要翻译： 本文公开了一种具有多个过滤板的过滤器的改进，所述过滤板以固定的间隔垂直间隔设置，以在其间插入过滤空间，并且将许多刮板从过滤板堆叠的轴线向外放置，并将每个过滤板插入过滤空间 即相邻的过滤板之间的改进，其包括给每个过滤板一个完美的圆形周边，以避免从周向形成任何突起，并且同时设置刮刀以便与相邻的过滤板保持滑动接触 滤板。

公开(公告)号：US08878336B2

公开(公告)日：2014-11-04

申请号：US13590581

申请日：2012-08-21

申请人： Makoto Yasuda ,  Kazuyoshi Arimura ,  Yoshiharu Kato

发明人： Makoto Yasuda ,  Kazuyoshi Arimura ,  Yoshiharu Kato

IPC分类号： H01L29/00 ,  H01L23/52 ,  H01L49/02 ,  H01L23/525 ,  H01L21/66

CPC分类号： H01L23/5256 ,  H01L22/22 ,  H01L23/5252 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse includes a first conductor, an insulating film on the first conductor, a second conductor on the insulating film, a first plug coupled to the first conductor, a second plug and a third plug each coupled to the second conductor, and a cover film formed on the second conductor and having tensile strength.

摘要翻译： 熔丝包括第一导体，第一导体上的绝缘膜，绝缘膜上的第二导体，耦合到第一导体的第一插头，每个耦合到第二导体的第二插头和第三插头，以及覆盖膜 形成在第二导体上并具有拉伸强度。

公开(公告)号：US20100254208A1

公开(公告)日：2010-10-07

申请号：US12818956

申请日：2010-06-18

申请人： Masami Nakashima ,  Yoshiharu Kato ,  Kazufumi Komura

发明人： Masami Nakashima ,  Yoshiharu Kato ,  Kazufumi Komura

IPC分类号： G11C7/00

CPC分类号： G11C29/50016 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/028 ,  G11C29/50 ,  G11C29/783 ,  G11C2207/2227 ,  G11C2211/4061 ,  G11C2211/4067

摘要： The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.

摘要翻译： 本发明提供一种由于适当的刷新稀疏功能而在待机状态下减少电流消耗的半导体存储器件及其刷新控制方法。 当刷新操作和外部访问操作彼此独立地执行时添加刷新稀疏功能时，刷新地址计数器输出刷新地址Add（C）并将预定的高位比特输入到刷新 - 作为高阶刷新地址的输出控制Add（C）（m），其中进行关于刷新操作的判断。 与判断结果相对应的刷新允许信号RFEN被输入到字驱动器以激活和控制字驱动器。 刷新稀疏控制电路的判断处理可嵌入行系统的访问时间。

公开(公告)号：US07764559B2

公开(公告)日：2010-07-27

申请号：US11715452

申请日：2007-03-08

申请人： Masami Nakashima ,  Yoshiharu Kato ,  Kazufumi Komura

发明人： Masami Nakashima ,  Yoshiharu Kato ,  Kazufumi Komura

IPC分类号： G11C7/00

CPC分类号： G11C29/50016 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/028 ,  G11C29/50 ,  G11C29/783 ,  G11C2207/2227 ,  G11C2211/4061 ,  G11C2211/4067

摘要： The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.

摘要翻译： 本发明提供一种由于适当的刷新稀疏功能而在待机状态下减少电流消耗的半导体存储器件及其刷新控制方法。 当刷新操作和外部访问操作彼此独立地执行时添加刷新稀疏功能时，刷新地址计数器输出刷新地址Add（C）并将预定的高位比特输入到刷新 - 作为高阶刷新地址的输出控制Add（C）（m），其中进行关于刷新操作的判断。 与判断结果相对应的刷新允许信号RFEN被输入到字驱动器以激活和控制字驱动器。 刷新稀疏控制电路的判断处理可嵌入行系统的访问时间。

公开(公告)号：US07562335B2

公开(公告)日：2009-07-14

申请号：US11583131

申请日：2006-10-19

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： G06F17/50

CPC分类号： H03K5/26 ,  G11C11/401 ,  G11C29/02 ,  G11C29/023 ,  Y10T307/74

摘要： An object is to provide a semiconductor device in which it is possible to determine whether or not a minute delay time given by a delay circuit is within a specified value or not, and a method of testing the semiconductor device. In response to a data strobe signal TDQS for testing, the delay circuits DC0 and DC1 produce delay data strobe signals IDQS0 and IDQS1 delayed by delay times DT0 and DT1. Outputted as a reverse signal from the inverter INV0, is a reverse data strobe signal RIDQS0 in response to the delay data strobe signal IDQS0, and delayed by an allowable delay time IT. Inputted into the NAND gate ND0, are the reverse data strobe signal RIDQS0 and the delay data strobe signal IDQS1. When, in comparison with the phase of the delay data strobe signal IDQS0, the phase of the delay data strobe signal IDQS1 is delayed by the allowable delay time IT or more, a pulse signal PL0 is not outputted from the NAND gate ND0.

摘要翻译： 目的是提供一种半导体器件，其中可以确定由延迟电路给出的微小延迟时间是否在规定值内，以及测试半导体器件的方法。 响应于用于测试的数据选通信号TDQS，延迟电路DC0和DC1产生延迟数据选通信号IDQS0和IDQS1延迟延迟时间DT0和DT1。 作为来自反相器INV0的反向信号输出，是响应于延迟数据选通信号IDQS0的反向数据选通信号RIDQS0，并延迟了允许的延迟时间IT。 输入到NAND门ND0中的是反向数据选通信号RIDQS0和延迟数据选通信号IDQS1。 当与延迟数据选通信号IDQS0的相位相比，延迟数据选通信号IDQS1的相位延迟可允许的延迟时间IT或更大时，不从NAND门ND0输出脉冲信号PL0。

公开(公告)号：US07440038B2

公开(公告)日：2008-10-21

申请号：US11166395

申请日：2005-06-23

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： H04N5/64

CPC分类号： F16M11/2014 ,  F16M11/10 ,  F16M2200/08 ,  H04N5/64 ,  Y10S248/919

摘要： There is disclosed a liquid crystal display apparatus including a main body and a swivel mechanism, where the main body is capable of smoothly swiveling. A countersunk hole is formed in a bottom plate member as follows: When a through-hole for inserting a screw is formed in a metal sheet to be a bottom plate member, there is also concurrently formed an accommodating hole for accommodating flow of the material forming the metal sheet upon plastic forming or pressing which is performed subsequently for forming a countersink, and then the countersink is formed at an open end of the through-hole by pressing. It is preferable that a plurality of the accommodating holes are formed around the through-hole.

摘要翻译： 公开了一种包括主体和旋转机构的液晶显示装置，其中主体能够平稳地旋转。 在底板构件中形成有埋头孔，如下所述：当金属板中形成用于插入螺钉的通孔作为底板构件时，还形成有用于容纳形成材料的流动的容纳孔 金属片在塑性成形或压制时随后进行以形成埋头孔，然后通过压制在通孔的开口端形成埋头孔。 优选地，在通孔周围形成有多个容纳孔。

公开(公告)号：US20070091678A1

公开(公告)日：2007-04-26

申请号：US11583129

申请日：2006-10-19

申请人： Yoshiharu Kato ,  Yoshihiro Takemae ,  Toshio Ogawa ,  Tetsuhiko Endoh ,  Yoshinori Okajima

发明人： Yoshiharu Kato ,  Yoshihiro Takemae ,  Toshio Ogawa ,  Tetsuhiko Endoh ,  Yoshinori Okajima

IPC分类号： G11C16/06

CPC分类号： G11C16/32 ,  G06F11/1068 ,  G11C7/1006 ,  G11C2029/0411 ,  G11C2207/104

摘要： A volatile memory has a volatile additional area for storing an error correction code for a nonvolatile memory. Data stored in the nonvolatile memory are transferred to the volatile memory together with the error correction code without making an error correction. Thus, data transfer time from the nonvolatile memory to the volatile memory can be shortened. As a result, it is possible to shorten the time from beginning of the data transfer from the nonvolatile memory to the volatile memory to a point at which data becomes accessible.

摘要翻译： 易失性存储器具有用于存储用于非易失性存储器的纠错码的易失性附加区域。 存储在非易失性存储器中的数据与错误校正码一起传送到易失性存储器，而不进行纠错。 因此，可以缩短从非易失性存储器到易失性存储器的数据传送时间。 结果，可以缩短从非易失性存储器到易失性存储器的数据传输开始到数据可访问的时间。

公开(公告)号：US07206246B2

公开(公告)日：2007-04-17

申请号：US11249454

申请日：2005-10-14

申请人： Masami Nakashima ,  Yoshiharu Kato ,  Kazufumi Komura

发明人： Masami Nakashima ,  Yoshiharu Kato ,  Kazufumi Komura

IPC分类号： G11C7/00

CPC分类号： G11C29/50016 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/028 ,  G11C29/50 ,  G11C29/783 ,  G11C2207/2227 ,  G11C2211/4061 ,  G11C2211/4067

摘要： The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.

公开(公告)号：US07028235B1

公开(公告)日：2006-04-11

申请号：US09494953

申请日：2000-02-01

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： G01R31/28

CPC分类号： G11C29/025 ,  G01R31/2853 ,  G11C29/02 ,  G11C29/36

摘要： A method of testing an electronic device including first and second semiconductor devices connected to each other with a plurality of bus lines. First, the first semiconductor device supplies a selected one of the bus lines with a first logical output signal. Then, the second semiconductor device acquires a first bus line signal from the selected bus line. The second semiconductor device inverts the first bus line signal to generate a second logical output signal. The second semiconductor device transmits the second logical output signal to the first semiconductor device. The first semiconductor device receives a second bus line signal from the selected bus line. The first semiconductor device compares the first logical output signal and the second bus line signal to detect a connection between the first semiconductor device and the second semiconductor device.

摘要翻译： 一种测试电子设备的方法，该电子设备包括用多个总线线路彼此连接的第一和第二半导体器件。 首先，第一半导体器件向所选择的总线线路提供第一逻辑输出信号。 然后，第二半导体器件从所选择的总线获取第一总线信号。 第二半导体器件使第一总线信号反相以产生第二逻辑输出信号。 第二半导体器件将第二逻辑输出信号发送到第一半导体器件。 第一半导体器件从所选择的总线接收第二总线信号。 第一半导体器件比较第一逻辑输出信号和第二总线信号以检测第一半导体器件和第二半导体器件之间的连接。

公开(公告)号：US20060001783A1

公开(公告)日：2006-01-05

申请号：US11166469

申请日：2005-06-23

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： H04N5/64

CPC分类号： H04N5/64 ,  F16M11/10 ,  F16M11/2014 ,  F16M2200/08

摘要： A liquid crystal display apparatus including a tilt mechanism, which is capable of preventing an inadvertent insertion of a finger of a user in a groove of a bracket of the tilt mechanism even while a cover for concealing the bracket is removed, wherein provided is a washer-like member or inadvertent-insertion preventer which has a through-hole or perforated portion through which a pawl formed in a mainbody bracket or one of two brackets is inserted, and is attached to the pawl at a position to contact a stand bracket or the other of the two brackets, by inserting the pawl through the through-hole. The washer-like member is preferably made of a plastic and sandwiched between the two brackets.

摘要翻译： 一种液晶显示装置，包括倾斜机构，其能够防止用户的手指无意插入倾斜机构的支架的凹槽中，即使在用于隐藏托架的盖子被移除时，其中设置有垫圈 其具有通孔或穿孔部分，通过该通孔或穿孔部分形成在主体托架中的​​棘爪或两个托架中的一个托架中的棘爪，并且在与支架支架或者支架支架接触的位置处附接到棘爪 通过将棘爪插入通孔中，两个支架中的另一个。 垫圈状构件优选地由塑料制成并夹在两个托架之间。