公开(公告)号：US20070216444A1

公开(公告)日：2007-09-20

申请号：US11542149

申请日：2006-10-04

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： H03K19/0175

CPC分类号： H03K19/0175

摘要： This invention provides an interface circuit for detecting that a DQS signal from a DDR SDRAM is at an intermediate potential. An interface circuit is connected to at least a signal line which transmits the DQS signal from the DDR SDRAM and reaches an intermediate potential VM when the signal attains an inactive state. The interface circuit has a comparing portion for comparing the potential of the DQS with a threshold potential VREFH which is a potential that is different from the intermediate potential VM.

摘要翻译： 本发明提供一种用于检测来自DDR SDRAM的DQS信号处于中间电位的接口电路。 接口电路至少连接到从DDR SDRAM发送DQS信号的信号线，并且当信号达到非活动状态时到达中间电位VM。 接口电路具有比较部分，用于将DQS的电位与作为不同于中间电位VM的电位的阈值电位VREFH进行比较。

公开(公告)号：US07251766B2

公开(公告)日：2007-07-31

申请号：US11198221

申请日：2005-08-08

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： G01R31/28 ,  H03K19/00

CPC分类号： G11C29/025 ,  G01R31/2853 ,  G11C29/02 ,  G11C29/36

摘要： A method of testing an electronic device including first and second semiconductor devices connected to each other with a plurality of bus lines. First, the first semiconductor device supplies a selected one of the bus lines with a first logical output signal. Then, the second semiconductor device acquires a first bus line signal from the selected bus line. The second semiconductor device inverts the first bus line signal to generate a second logical output signal. The second semiconductor device transmits the second logical output signal to the first semiconductor device. The first semiconductor device receives a second bus line signal from the selected bus line. The first semiconductor device compares the first logical output signal and the second bus line signal to detect a connection between the first semiconductor device and the second semiconductor device.

摘要翻译： 一种测试电子设备的方法，该电子设备包括用多个总线线路彼此连接的第一和第二半导体器件。 首先，第一半导体器件向所选择的总线线路提供第一逻辑输出信号。 然后，第二半导体器件从所选择的总线获取第一总线信号。 第二半导体器件使第一总线信号反相以产生第二逻辑输出信号。 第二半导体器件将第二逻辑输出信号发送到第一半导体器件。 第一半导体器件从所选择的总线接收第二总线信号。 第一半导体器件比较第一逻辑输出信号和第二总线信号以检测第一半导体器件和第二半导体器件之间的连接。

公开(公告)号：US20070091989A1

公开(公告)日：2007-04-26

申请号：US11583130

申请日：2006-10-19

申请人： Yoshiharu Kato ,  Yoshihiro Takemae ,  Toshio Ogawa ,  Tetsuhiko Endoh ,  Yoshinori Okajima

发明人： Yoshiharu Kato ,  Yoshihiro Takemae ,  Toshio Ogawa ,  Tetsuhiko Endoh ,  Yoshinori Okajima

IPC分类号： H04L5/16 ,  H04L25/00

CPC分类号： H04L25/0282 ,  H04L5/04 ,  H04L25/0294

摘要： Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the currents generated by the transmitter units, and propagates them to a receiver unit as a synthetic current. The receiver unit restores the logical values the transmitter units generated, in accordance with the synthetic current. The values of the currents the transmitter units generate in correspondence with the logical values each differ, so that the value of the synthetic current can be changed for every combination of logical values. Accordingly, the receiver unit can restore the logical values outputted from the respective transmitter units, based on the synthetic current. That is, employing the common signal line enables signals transmitted from the transmitter units to be simultaneously received. Consequently, the number of signal lines laid between the transmitter units and the receiver unit is reduced.

摘要翻译： 多个发射机单元分别产生对应于多个逻辑值的多个电流，并将电流传播到公共信号线。 公共信号线合成由发射机单元产生的电流，并将其作为合成电流传播到接收机单元。 接收器单元根据合成电流恢复发射机单元产生的逻辑值。 发射机单元对应​​于逻辑值产生的电流值各自不同，使得可以针对逻辑值的每个组合来改变合成电流的值。 因此，接收机单元可以基于合成电流来恢复从各个发射机单元输出的逻辑值。 也就是说，采用公共信号线使得能够同时接收从发送单元发送的信号。 因此，放置在发射机单元和接收机单元之间的信号线的数量减少。

公开(公告)号：US07135882B2

公开(公告)日：2006-11-14

申请号：US11090661

申请日：2005-03-28

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： G01R31/26

CPC分类号： G11C16/20 ,  G11C29/1201 ,  G11C29/44 ,  G11C2029/4402 ,  H04N5/232 ,  H04N5/2353

摘要： It is intended to provide a semiconductor integrated circuit device permitting reading of information specific to chips within the mounted chips while restraining the increase in the total number of terminals of the package and enabling the area of circuits required for reading information specific to chips to be made smaller than that according to the prior art, and a control method therefor. The same terminal is used as the external terminal to which the pulse signals are inputted and the external terminal from which the chip-specific information is outputted. Also, the external terminal for inputting/outputting required power supply in the normal operation mode and the external terminal for reading chip-specific information in the information reading mode are used in common. The increase in the number of external terminals can be thereby restrained. Moreover, the counter unit is shared between functional circuits and the comparative decision unit. This can serve to restrain the increase in chip area.

摘要翻译： 旨在提供一种半导体集成电路装置，允许读取安装的芯片内的芯片的信息，同时抑制封装的端子总数的增加，并且使得能够制作读取芯片特有的信息所需的电路区域 小于根据现有技术的控制方法。 使用相同的端子作为输入脉冲信号的外部端子和从其输出芯片特定信息的外部端子。 此外，共同使用用于在正常操作模式下输入/输出所需电源的外部端子和用于在信息读取模式中读取芯片特定信息的外部端子。 由此可以抑制外部端子的数量的增加。 此外，计数器单元在功能电路和比较判定单元之间共享。 这可以抑制芯片面积的增加。

公开(公告)号：US07133996B2

公开(公告)日：2006-11-07

申请号：US10279963

申请日：2002-10-25

申请人： Shinichiro Ikeda ,  Yoshiharu Kato

发明人： Shinichiro Ikeda ,  Yoshiharu Kato

IPC分类号： G06F12/06

CPC分类号： G11C11/4076 ,  G11C11/4074 ,  G11C11/4087

摘要： A memory device for ensuring efficient access and reduction in current consumption. The memory device includes a plurality of memory cells arranged in accordance with a first address and a second address which define a logical address map indicating a logical shape of the memory array. An address map changing unit is operatively coupled to the memory array, for receiving a first address signal for generating the first address and a second address signal for generating the second address. The address map changing unit is capable of changing the logical address map by altering a part of one of the first address signal and the second address signal.

公开(公告)号：US06942157B2

公开(公告)日：2005-09-13

申请号：US10241979

申请日：2002-09-11

申请人： Tohru Nozawa ,  Yoshiharu Kato

发明人： Tohru Nozawa ,  Yoshiharu Kato

IPC分类号： G06K19/07 ,  H01L21/822 ,  H01L27/04 ,  H01Q1/38 ,  H05K1/02 ,  H05K1/18 ,  G06K19/06

CPC分类号： H05K1/0274 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/181 ,  H05K2201/10734

摘要： An IC chip is provided with a wireless unit for inputting and outputting data by wireless communication, in addition to a logic section, so that the IC chip no longer needs I/O pads, leaving only power supply and ground pads. IC chips can input and output data with one another by wireless communications, which makes it possible to significantly improve the spacing relationships of various chips on a singular or even plurality of substrates.

摘要翻译： 除了逻辑部分之外，IC芯片还具有用于通过无线通信输入和输出数据的无线单元，使得IC芯片不再需要I / O焊盘，仅留下电源和接地焊盘。 IC芯片可以通过无线通信彼此输入和输出数据，这使得可以显着地改善单个或甚至多个基板上各种芯片的间隔关系。

公开(公告)号：US20050157585A1

公开(公告)日：2005-07-21

申请号：US10853313

申请日：2004-05-26

申请人： Yoshiharu Kato ,  Gen Tsukishiro ,  Yoshihiro Takemae

发明人： Yoshiharu Kato ,  Gen Tsukishiro ,  Yoshihiro Takemae

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F13/42 ,  G11C8/00 ,  G11C11/406

CPC分类号： G06F13/4243 ,  G11C11/406 ,  Y02D10/14 ,  Y02D10/151

摘要： It is intended to provide a memory control device and memory control method capable of reducing charge/discharge current consumed while various commands are inputted to a semiconductor memory device and reducing occurrence of power noises. During periods TT1, TT2, and TT3 which are parts of a period tCKE in which a clock enable signal CKE is in active state, supply of a control clock SD_CLK from a memory control device 1 to a synchronous-type semiconductor memory device 12 can be stopped. Furthermore, in case an input of a data input/output period of an external command and that of refresh operation period of a refresh command RCMD overlap and an access region of the external command and that of the refresh command RCMD do not coincide, those commands are converted to control command signal SD_CMD in parallel, whereby parallel conversion processing operation can be conducted.

摘要翻译： 旨在提供一种存储器控制装置和存储器控制方法，其能够在将各种命令输入到半导体存储器件中时减少所消耗的充电/放电电流并减少电力噪声的发生。 在时钟使能信号CKE处于活动状态的周期tCKE的一部分的时段TT 1，TT 2和TT 3期间，将控制时钟SD_CLK从存储器控制装置1提供给同步型半导体存储器件 12可以停止。 此外，在外部命令的数据输入/输出周期的输入和刷新命令RCMD的刷新操作周期的输入与外部命令的访问区域和刷新命令RCMD的访问区域不重合的情况下，这些命令 被并行地转换为控制指令信号SD_CMD，由此可以进行并行转换处理操作。

公开(公告)号：US06501691B2

公开(公告)日：2002-12-31

申请号：US09768459

申请日：2001-01-25

申请人： Satoru Kawamoto ,  Motoki Mizutani ,  Shinji Nagai ,  Yoshiharu Kato

发明人： Satoru Kawamoto ,  Motoki Mizutani ,  Shinji Nagai ,  Yoshiharu Kato

IPC分类号： G11C700

CPC分类号： G11C29/025 ,  G11C17/14 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/0403

摘要： A semiconductor memory device having a burn-in test capability. The semiconductor memory device includes a detection circuit, which is connected to the plurality of word lines. The detection circuit detects whether a stress voltage for a burn-in test has been applied to all of the word lines along their entire lengths in the burn-in test.

摘要翻译： 具有老化测试能力的半导体存储器件。 半导体存储器件包括连接到多个字线的检测电路。 检测电路检测在老化测试中，老化测试的应力电压是否已沿其整个长度应用于所有字线。

公开(公告)号：US06452854B1

公开(公告)日：2002-09-17

申请号：US09946561

申请日：2001-09-06

申请人： Yoshiharu Kato ,  Isamu Kobayashi

发明人： Yoshiharu Kato ,  Isamu Kobayashi

IPC分类号： G11C700

CPC分类号： G11C5/147 ,  H01L27/092 ,  H01L27/10897

摘要： A power supply circuit for supplying a semiconductor memory device with power to perform refreshing. The power supply circuit is connected to an external power supply. The power supply circuit includes a first power supply circuit, which generates a step down voltage by decreasing a first voltage on the external power supply in a normal operation mode, a second power supply circuit, which supplies the internal circuit with a second voltage on the external power supply in a self-refresh mode, and a detection circuit, which detects entry to the self-refresh mode and a voltage level of the external power supply and generates a detection signal based on the detection. During the self-refresh mode, the first power supply circuit receives the second voltage from the external power supply, and the first and second power supply circuits supply the internal circuit with the second voltage based on the detection signal.

摘要翻译： 一种用于向半导体存储器件提供电力以执行刷新的电源电路。 电源电路连接到外部电源。 电源电路包括第一电源电路，其通过在正常操作模式中减小外部电源上的第一电压来产生降压电压;第二电源电路，其向内部电路提供第二电压， 以及检测电路，其检测进入自刷新模式和外部电源的电压电平，并且基于该检测产生检测信号。 在自刷新模式期间，第一电源电路从外部电源接收第二电压，并且第一和第二电源电路基于检测信号向内部电路提供第二电压。

公开(公告)号：US06418072B2

公开(公告)日：2002-07-09

申请号：US09750352

申请日：2000-12-29

申请人： Yoshichika Nakaya ,  Shinichiro Ikeda ,  Yoshiharu Kato ,  Satoru Kawamoto

发明人： Yoshichika Nakaya ,  Shinichiro Ikeda ,  Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C700

CPC分类号： G11C29/40

摘要： The first switching circuit selects data of a predetermined bit from the input/output data in accordance with each of a plurality of testing modes and outputs the selected data as testing data. The second switching circuits receive the testing data and each bit of the input/output data, and select one of the input/output data and the testing data in accordance with the operation mode. In detail, each bit of the input/output data is respectively outputted to the memory cells during normal operation mode, and during testing mode the testing data is selected to be outputted to the memory cells as the common input/output data. Thus, write control for multiple kinds of data compressing test can be performed by using the simple first and second switching circuits. As a result, the control circuit for the data compressing test can be reduced in layout size.

摘要翻译： 第一开关电路根据多个测试模式中的每一个从输入/输出数据中选择预定位的数据，并输出所选择的数据作为测试数据。 第二开关电路接收测试数据和输入/输出数据的每一位，并根据操作模式选择输入/输出数据和测试数据之一。 详细地说，输入/输出数据的每一位在正常操作模式下分别输出到存储单元，在测试模式期间，选择测试数据作为公共输入/输出数据输出到存储单元。 因此，可以通过使用简单的第一和第二开关电路来执行用于多种数据压缩测试的写入控制。 结果，可以减少用于数据压缩测试的控制电路的布局尺寸。