公开(公告)号：US07034815B2

公开(公告)日：2006-04-25

申请号：US10071409

申请日：2002-02-08

Applicant: Greg Neal

Inventor： Greg Neal

IPC: G09G5/00

CPC classification number: G09G5/008 ,  G09G5/006 ,  G09G5/18 ,  G09G2340/0421

Abstract: A method, system and apparatus for synchronizing an analog video signal to an LCD monitor is described. For each of a succession of associated video frames are surveyed for a number of displayed features based upon a pseudo-random selection of regions into which the displayed video frame is divided. During successive associated video frames, a minimum number of features each is which is generated by an associated pixel clock is determined based upon a pre-selected number of scans. Subsequent to the determination of the minimum number of features, a transition region for each of plurality of horizontal resolution values is determined by scanning through a selected number of pixel clock phases. Based upon a minimum transition zone corresponding to a maximum change in the number of features for a particular pixel clock phase, an associated horizontal resolution is provided.

公开(公告)号：US07034722B2

公开(公告)日：2006-04-25

申请号：US10904143

申请日：2004-10-26

Applicant: John Thomas

Inventor： John Thomas

IPC: H03M1/10 ,  H04N17/00 ,  H04N17/02

CPC classification number: G09G3/20 ,  G09G3/2011 ,  G09G2320/041 ,  G09G2320/0666

Abstract: In digital display circuitry, configured to display an image encoded in an analog display signal, the digital display circuitry includes analog-to-digital converter (ADC) circuitry to recover pixel data elements of the image. During vertical blanking intervals of the analog display signal, the ADC circuitry is calibrated. Outside the vertical blanking intervals, the ADC circuitry is used to convert information in the analog display signal into digital representations of the pixel data elements. For example, the calibrating may include determining more acceptable values for certain ones of the operational parameters of the ADC circuitry.

Abstract translation: 在被配置为显示以模拟显示信号编码的图像的数字显示电路中，数字显示电路包括用于恢复图像的像素数据元素的模数转换器（ADC）电路。 在模拟显示信号的垂直消隐间隔期间，对ADC电路进行校准。 在垂直消隐间隔之外，ADC电路用于将模拟显示信号中的信息转换成像素数据元素的数字表示。 例如，校准可以包括确定ADC电路的某些操作参数的更可接受的值。

公开(公告)号：US20060083425A1

公开(公告)日：2006-04-20

申请号：US11044755

申请日：2005-01-26

Applicant: Caba Moldvai

Inventor： Caba Moldvai

IPC: G06K9/00

CPC classification number: H04N1/4074 ,  G06T5/009 ,  G06T5/40 ,  G09G3/20 ,  G09G2320/066 ,  G09G2360/16

Abstract: Disclosed is a method for generating transfer curves for adaptive contrast enhancement. Given an input image, a luminance histogram is generated based on a set of predefined input luminance ranges. The luminance histogram is then expressed as a weighted sum of a set of predefined “primitive” histograms. Each primitive histogram has an associated reference transfer curve. A final transfer curve is produced as a corresponding weighted sum of the associated reference transfer curves. The image luminance can then be adjusted according the to the final transfer curve, resulting in enhanced image contrast. The disclosed method enables expansion of the number of available reference transfer curves without increasing the number of luminance ranges.

Abstract translation: 公开了一种用于产生自适应对比度增强的传输曲线的方法。 给定输入图像，基于一组预定义的输入亮度范围来生成亮度直方图。 然后将亮度直方图表示为一组预定义的“原始”直方图的加权和。 每个基本直方图都有相关的参考传输曲线。 产生最终转移曲线作为相关参考转移曲线的对应加权和。 然后可以根据最终传输曲线调整图像亮度，从而增强图像对比度。 所公开的方法能够扩大可用参考传送曲线的数量而不增加亮度范围的数量。

公开(公告)号：US20060082584A1

公开(公告)日：2006-04-20

申请号：US11060862

申请日：2005-02-18

Applicant: Ali Noorbakhsh ,  David Keene ,  John Lattanzi ,  Ram Chilukuri

Inventor： Ali Noorbakhsh ,  David Keene ,  John Lattanzi ,  Ram Chilukuri

IPC: G09G5/39

CPC classification number: G09G5/006 ,  G09G2370/047

Abstract: In a VESA standard compliant display controller having a processor arranged to process executable instructions and associated data, a memory device arranged to store EDID and the executable instructions and associated data, a number of data ports coupled to the memory device by way of an 12C data bus each coupled to a host device, a method of transferring EDID from the memory device over the 12C data bus to a requesting one of the data ports while servicing a processor memory access request without clock stretching.

Abstract translation: 在具有被配置为处理可执行指令和相关联的数据的处理器的VESA标准兼容显示控制器中，布置成存储EDID和可执行指令和相关数据的存储器设备，通过12C数据耦合到存储器设备的多个数据端口 每个都耦合到主机设备的一个总线，一种通过12C数据总线将EDID从存储器件传送到请求的一个数据端口的方法，同时服务于没有时钟延伸的处理器存储器访问请求。

公开(公告)号：US20060077306A1

公开(公告)日：2006-04-13

申请号：US11237606

申请日：2005-09-27

Applicant: Jayakanth Suyambukesan ,  Peter Swartz ,  Xu Dong

Inventor： Jayakanth Suyambukesan ,  Peter Swartz ,  Xu Dong

IPC: H04N5/14

CPC classification number: H04N5/144 ,  H04N5/142

Abstract: Frequency content motion detection is performed by decomposing a raw field luminance data in to a number of frequency content sub-bands, detecting motion using the raw field luminance data in parallel with the decomposing, generating a motion correction value by multiplying absolute values of the sub-bands by weighting factors, and applying the motion correction value to detected motion.

Abstract translation: 通过将原始场亮度数据分解成多个频率内容子带来进行频率内容运动检测，使用原始场亮度数据与分解并行地检测运动，通过乘以副的绝对值来生成运动校正值 通过加权因子，并且将运动校正值应用于检测到的运动。

公开(公告)号：US20050285815A1

公开(公告)日：2005-12-29

申请号：US11021635

申请日：2004-12-22

Applicant: John Tryhub ,  Steve Selby

Inventor： John Tryhub ,  Steve Selby

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3648 ,  G09G5/003 ,  G09G2320/0252 ,  G09G2320/0261 ,  G09G2320/103 ,  G09G2340/0435

Abstract: Reducing fast motion artifacts in an LCD panel by receiving a video stream at a first frame rate which is then downsampled to a second frame rate. The downsampled video stream is then upsampled to a third frame rate and a voltage is applied to a pixel element such that the pixel element transitions from a first pixel value to a predetermined second pixel value within a period of time consistent with the third frame rate.

Abstract translation: 通过以第一帧速率接收视频流来降低LCD面板中的快速运动伪影，然后以第二帧速率对其进行下采样。 下采样的视频流然后被上采样到第三帧速率，并且将电压施加到像素元件，使得像素元件在与第三帧速率一致的时间段内从第一像素值转换到预定的第二像素值。

公开(公告)号：US06933937B2

公开(公告)日：2005-08-23

申请号：US10640699

申请日：2003-08-13

Applicant: Sandeep Agarwal ,  Arun Johary

Inventor： Sandeep Agarwal ,  Arun Johary

IPC: G09G3/20 ,  G09G5/00

CPC classification number: G09G5/008

Abstract: Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency an optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from exsisting methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.

Abstract translation: 像素时钟频率和最佳采样相位调整是具有模拟视频接口的平板显示监视器（FPDM）的重要要求。 本发明提出了一种新的更先进的频率最佳采样相位确定方法。 它是基于分析图像的内容，通过直接优化图像质量达到相位和频率的最佳值。 该方法与两种计数方法不同。 首先，不需要有关预期频率的精确值的假设。 第二，代替跟随第一确定频率然后相位的两步法，本发明使单通道相频优化成为可能。

公开(公告)号：US20050055515A1

公开(公告)日：2005-03-10

申请号：US10969557

申请日：2004-10-19

Applicant: Richard Greicar

Inventor： Richard Greicar

IPC: G06F9/445 ,  G06F9/46 ,  G06F12/08 ,  G06F12/00

CPC classification number: G06F9/52 ,  G06F9/44521 ,  G06F9/44557

Abstract: A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which can be loaded individually into the local memory for execution. Queuing the individual blocks of code allows the program to be executed by the processor and also facilitates loading of the subsequent code to be executed. A semaphore system can be utilized to indicate which blocks of local memory are available/unavailable. The system can support the interaction of multiple independent programs in external memory.

公开(公告)号：US20040221056A1

公开(公告)日：2004-11-04

申请号：US10726440

申请日：2003-12-02

Applicant: Genesis Microchip Inc.

Inventor： Osamu Kobayashi

IPC: G06F015/16

CPC classification number: G06F3/14 ,  G09G5/006 ,  G09G2370/04 ,  H04L1/0002 ,  H04L5/1415 ,  H04L5/1446 ,  H04L25/4904 ,  H04N11/042 ,  Y02D50/10

Abstract: A method and apparatus of optimizing transmission (both real time and continuous) of a number of multimedia data packets between a multimedia source device and a multimedia display device is disclosed. In the described embodiment, the multimedia source device and the display device are coupled by way of a unidirectional main link arranged to carry the multimedia data packets from the multimedia source device and the multimedia display device and a bi-directional auxiliary channel arranged to transfer information between the multimedia source device and the multimedia display device. The method can be carried out by following at least the following operations. Providing a test pattern by the multimedia source device on the main link, determining a transmission quality factor of the main link based upon the test pattern, and optimizing the transmission of the multimedia data packets based upon the transmission quality factor.

Abstract translation: 公开了一种在多媒体源设备和多媒体显示设备之间优化多个多媒体数据分组的传输（包括实时和连续的）的方法和装置。 在所描述的实施例中，多媒体源设备和显示设备通过布置成承载来自多媒体源设备和多媒体显示设备的多媒体数据分组的单向主链路和布置成传送信息的双向辅助信道 在多媒体源设备和多媒体显示设备之间。 该方法可以通过以下操作进行至少以下操作。 通过主链路上的多媒体源设备提供测试模式，基于测试模式确定主链路的传输质量因子，并且基于传输质量因子优化多媒体数据分组的传输。

公开(公告)号：US5550764A

公开(公告)日：1996-08-27

申请号：US413895

申请日：1995-03-30

Applicant: Peter Mandl

Inventor： Peter Mandl

IPC: H03H17/06 ,  G06F17/10

CPC classification number: H03H17/0664

Abstract: A decimator for effecting a X:1 decimation, where X=is any positive integer greater than 1, comprising a FIR filter for receiving and filtering an input stream of data bits and in response generating a like number of filtered output data bits; and a hold circuit for sampling and outputting every Xth one of the filtered output data bits.

Abstract translation: 用于进行X：1抽取的抽取器，其中X =是大于1的任何正整数，包括用于接收和过滤数据位的输入流的FIR滤波器，并且响应于产生相似数目的滤波输出数据位; 以及保持电路，用于对每个第十个滤波输出数据位进行采样和输出。