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    Wireless communication chip that makes both 5 GHz band and 6 GHz band support two transmit and two receive paths
    61.
    发明授权
    Wireless communication chip that makes both 5 GHz band and 6 GHz band support two transmit and two receive paths 有权

    公开(公告)号：US11705934B2

    公开(公告)日：2023-07-18

    申请号：US17534435

    申请日：2021-11-23

    申请人： Realtek Semiconductor Corp.

    发明人： Hao-Han Hsu ,  Chung-Yao Chang

    IPC分类号： H04B1/58 ,  H04B1/44

    CPC分类号： H04B1/58 ,  H04B1/44

    摘要： A wireless communication chip includes an analog front-end circuit and a baseband circuit. The analog front-end circuit includes a first transceiver circuit and a second transceiver circuit, wherein the first transceiver circuit is arranged to transmit or receive signals through a first antenna, and the second transceiver circuit is arranged to transmit or receive signals through a second antenna. The baseband circuit is arranged to control the first transceiver circuit to use a first band or a second band for communication, and/or to control the second transceiver circuit to use the first band or the second band for communication. The baseband circuit controls the first transceiver circuit and the second transceiver circuit so that the analog front-end circuit alternately performs 2T2R in the first band and 2T2R in the second band.

    Chip and associated chip system
    62.
    发明授权
    Chip and associated chip system 有权

    公开(公告)号：US11694743B2

    公开(公告)日：2023-07-04

    申请号：US17340062

    申请日：2021-06-06

    申请人： Realtek Semiconductor Corp.

    发明人： Ching-Sheng Cheng

    IPC分类号： G11C16/04 ,  G11C11/408 ,  G06F13/42

    CPC分类号： G11C11/408 ,  G06F13/4221

    摘要： A chip system includes a first chip, a first DRAM, a second chip and a second DRAM. The first chip includes a first DRAM controller and a first serial transmission interface. The first DRAM is coupled to the first DRAM controller. The second chip includes a second DTAM controller and a second serial transmission interface. The second serial transmission interface is coupled to the first serial transmission interface. The second DRAM is coupled to the second DRAM controller. When the first chip intends to store first data and second data, the first chip stores the first data into the first DRAM via the first DRAM controller, and transmits the second data to the second chip via the first serial transmission interface; and the second chip stores the second data into the second DRAM via the second DRAM controller.

    COMPRESSION METHOD AND ASSOCIATED ELECTRONIC DEVICE
    64.
    发明公开
    COMPRESSION METHOD AND ASSOCIATED ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20230206389A1

    公开(公告)日：2023-06-29

    申请号：US18088794

    申请日：2022-12-27

    申请人： Realtek Semiconductor Corp.

    发明人： Tsung-Hsuan Li ,  Wan-Ju Tang ,  Shih-Tse Chen

    IPC分类号： G06T3/40 ,  G06T9/00

    CPC分类号： G06T3/40 ,  G06T9/00

    摘要： The present invention provides a compression method, wherein the compression method includes the steps of: setting a quantization function; setting a plurality of scaling ratios; receiving image data; for a block of a frame of the image data, using a conversion matrix to convert data of the block to generate a plurality of converted data; determining a specific scaling ratio from the plurality of scaling ratios according to the plurality of converted data; and using the quantization function to perform a quantization operation on a plurality of adjusted data to generate compressed data, wherein the plurality of adjusted data are generated according to the plurality of converted data and the specific scaling ratio.

    POWER CAPABILITY DETERMINATION DEVICE, ELECTRONIC DEVICE, AND POWER CAPABILITY DETERMINATION METHOD
    65.
    发明公开
    POWER CAPABILITY DETERMINATION DEVICE, ELECTRONIC DEVICE, AND POWER CAPABILITY DETERMINATION METHOD 审中-公开

    公开(公告)号：US20230204635A1

    公开(公告)日：2023-06-29

    申请号：US17743472

    申请日：2022-05-13

    申请人： Realtek Semiconductor Corp.

    发明人： Yueh-Hsing Huang ,  Sen-Huang Tang

    IPC分类号： H02J3/14 ,  G01R19/165

    CPC分类号： H02J3/14 ,  G01R19/16538

    摘要： A power capability determination device is arranged to determine a power capability of a power source, and includes a connector, a load circuit, a switch circuit, a voltage monitor circuit, and a processing circuit. The connector is arranged to receive the power source to output an input voltage at a power output terminal. The switch circuit is electrically connected between the load circuit and the power output terminal. The voltage monitor circuit is electrically connected to the power output terminal, and is arranged to monitor the input voltage to generate a monitored voltage value. The processing circuit is electrically connected to the voltage monitor circuit and the switch circuit, and is arranged to control the switch circuit, and in a state of controlling the switch circuit, receive the monitored voltage value and determine the power capability of the power source according to the monitored voltage value.

    Method for switching audiovisual interfaces and circuit system
    66.
    发明授权
    Method for switching audiovisual interfaces and circuit system 有权

    公开(公告)号：US11689762B2

    公开(公告)日：2023-06-27

    申请号：US17695329

    申请日：2022-03-15

    申请人： REALTEK SEMICONDUCTOR CORP.

    发明人： Chun-Chieh Chan ,  Ming-An Wu ,  Hung-Shao Chen

    IPC分类号： H04N21/4363 ,  H04N21/41

    CPC分类号： H04N21/43635 ,  H04N21/4104

    摘要： A method for switching audio-visual interfaces and a circuit system are provided. The circuit system is disposed in a sink device. A protocol layer circuit of each of audio-visual interfaces in the sink device includes a status and control data channel control module, which is used to respond to the signals sent by the video sources continuously when the sink device is connected with audio-visual sources via the audio-visual interfaces. The multiple video sources can accordingly send FRL (fixed rate link) signals to the sink device in response to responses made by the sink device. The protocol layer circuit includes an FRL audio-visual packet detection module that starts to detect a rate of an FRL and resolve audio-visual packets for obtaining audio-visual data for the audio-visual interface that the sink device switches to.

    Wireless Device for Achieving Low Latency Transmission of Time-Sensitive Data
    67.
    发明公开
    Wireless Device for Achieving Low Latency Transmission of Time-Sensitive Data 审中-公开

    公开(公告)号：US20230189327A1

    公开(公告)日：2023-06-15

    申请号：US17847198

    申请日：2022-06-23

    申请人： Realtek Semiconductor Corp.

    发明人： Chung-Yao Chang ,  Chuan-Hu Lin

    IPC分类号： H04W72/12 ,  H04L47/62 ,  H04L47/56

    CPC分类号： H04W72/1242 ,  H04L47/6215 ,  H04L47/56

    摘要： A wireless device includes a time-sensitive queue, an access category queue, a controller, and a transmitter. The access category queue is associated with an access category and a link. The controller is coupled to the access category queue, and is used to acquire a transmission opportunity according to a set of contention parameters of the access category. The transmitter is coupled to the controller and the time-sensitive queue, and is used to when a transmission opportunity is acquired, if the time-sensitive queue contains data, generate a data frame according to the data in the time-sensitive queue, and transmit the data to another wireless device via a link.