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公开(公告)号：US20210409023A1
公开(公告)日：2021-12-30
申请号：US17473012
申请日：2021-09-13
申请人： KIOXIA CORPORATION
IPC分类号： H03K19/0175 , H01L23/538
摘要： A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.
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公开(公告)号：US11201622B2
公开(公告)日：2021-12-14
申请号：US17157605
申请日：2021-01-25
发明人： Kazuma Sakato , Yohei Horikawa
IPC分类号： H03K19/0175 , G06F1/08 , G06F7/57
摘要： The invention provides an apparatus comprising a programmable circuit including a plurality of 2-input 1-output ALUs, and an updating unit updating the programmable circuit according to circuit information, wherein each of the ALUs includes a calculation unit which performs a set type of calculation for two data and output a calculation result, a delay unit which delays the two input data in accordance with delay amounts independently set and supplies the delayed data to the calculation unit, and a controller which controls a delay amount for the delay unit and a calculation timing for the calculation unit in accordance with externally set information, wherein the updating unit sets clock gating start timings for a plurality of delay elements of the delay unit if an ALU of interest as a first processing circuit in the programmable circuit inputs final data to be processed.
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公开(公告)号：US11196393B2
公开(公告)日：2021-12-07
申请号：US17027728
申请日：2020-09-22
发明人： Ting-Yuan Cheng
IPC分类号： G05F1/46 , G05F1/56 , H03K5/24 , H03F3/04 , H03K19/0175
摘要： An amplifying apparatus and a voltage-to-current conversion apparatus are provided. The amplifying apparatus includes a zero point generating circuit, a level shift circuit, a transistor, and an amplifying circuit. A first terminal of the zero point generating circuit is coupled to an output terminal of the amplifying apparatus. A first terminal of the level shift circuit is coupled to the output terminal of the amplifying apparatus. A first terminal of the transistor is coupled to a supply voltage. A second terminal of the transistor is coupled to the output terminal of the amplifying apparatus. A control terminal of the transistor is coupled to a second terminal of the level shift circuit. An input terminal of the amplifying circuit is coupled to an input terminal of the amplifying apparatus. An output terminal of the amplifying circuit is coupled to the output terminal of the amplifying apparatus.
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公开(公告)号：US11152924B2
公开(公告)日：2021-10-19
申请号：US16910261
申请日：2020-06-24
发明人： Kwang Chan Lee , Hyoungseok Oh , Jungwook Heo
IPC分类号： H03K19/0175 , H03K3/356 , H03K19/0185
摘要： A level shifter including an input block that receives an input voltage swinging between a first ground voltage and a first power supply voltage and that connects one node of a first node and a second node to a first ground node, in response to the input voltage, a shifting block that mutually exchanges the voltage levels of third and fourth nodes in response to a current flowing through the one node, a pulse generator that generates a first pulse and a second pulse in response to the input voltage, a first transistor that directly connects the third node to the first ground node in response to the first pulse, and a second transistor that directly connects the fourth node to the first ground node in response to the second pulse.
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公开(公告)号：US11146056B2
公开(公告)日：2021-10-12
申请号：US15931187
申请日：2020-05-13
发明人： Yu-Jen Cheng , Chih-Wei Mu , Sheng-Tsung Chen , Chieh-Min Lo , Wei-Chung Chang
IPC分类号： H02H3/26 , H03K19/0175 , H02H1/00
摘要： An interface control circuit complying with an interface specification includes: an interface signal transceiver circuit and a protection circuit. The interface signal transceiver circuit is coupled to a first interface connection pin and a second interface connection pin of a first interface connector circuit. The interface signal transceiver circuit is for transmitting and/or receiving an interface signal according to the interface specification. When the interface signal transceiver circuit operates under a first state, the protection circuit determines whether a foreign object exists between the first interface connection pin and the second interface connection pin according to a voltage change or a current change at the second interface connection pin. Under the first state, the interface signal transceiver circuit generates a pull-up signal and a pull-down signal which are toggled with each other at the first interface connection pin.
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公开(公告)号：US20210305984A1
公开(公告)日：2021-09-30
申请号：US17303986
申请日：2021-06-11
发明人： Markku ROUVALA , Helena POHJONEN , Vuokko LANTZ
摘要： An apparatus and method wherein the apparatus comprises; a sensor arrangement comprising a plurality of sensor cells wherein a sensor cell comprises a transistor and a sensor coupled to the transistor; first selection circuitry configured to sequence a subset of sensor cells to which a gate input signal is provided, wherein the gate input signal is provided to the gate of the transistors within the sensor cells; second selection circuitry configured to sequence a subset of sensor cells from which an output signal is received; sensing signal circuitry configured to provide a sensing signal, wherein the sensors are provided between the sensing signal circuitry and the second selection circuitry such that the output signal provides an indication of the impedance of the sensors.
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公开(公告)号：US11115022B2
公开(公告)日：2021-09-07
申请号：US15148700
申请日：2016-05-06
发明人： Jie Gu
IPC分类号： G06F1/26 , H03K3/03 , H03K5/24 , H03K19/0175 , H03K3/356
摘要： An accelerated aging circuit is described to shorten the required stress time to a few seconds of operation. Due to the challenges posed by process variation in advanced CMOS technology, a stochastic processing methodology is also described to reduce the failure rate of the tracking and detection. Combining both circuit and system level acceleration, the creation of a silicon marker can be realized within seconds of usage in contrast with days of operation from previously reported aging monitor.
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公开(公告)号：US20210234543A1
公开(公告)日：2021-07-29
申请号：US17157605
申请日：2021-01-25
发明人： Kazuma Sakato , Yohei Horikawa
IPC分类号： H03K19/0175 , G06F7/57 , G06F1/08
摘要： The invention provides an apparatus comprising a programmable circuit including a plurality of 2-input 1-output ALUs, and an updating unit updating the programmable circuit according to circuit information, wherein each of the ALUs includes a calculation unit which performs a set type of calculation for two data and output a calculation result, a delay unit which delays the two input data in accordance with delay amounts independently set and supplies the delayed data to the calculation unit, and a controller which controls a delay amount for the delay unit and a calculation timing for the calculation unit in accordance with externally set information, wherein the updating unit sets clock gating start timings for a plurality of delay elements of the delay unit if an ALU of interest as a first processing circuit in the programmable circuit inputs final data to he processed,
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公开(公告)号：US11075624B2
公开(公告)日：2021-07-27
申请号：US16906664
申请日：2020-06-19
IPC分类号： H03K19/0185 , H03K17/16 , H03K19/20 , H03K19/0175
摘要： A hybrid driver receives complementary high-speed input data signals and a pair of low-speed input data signals and selects one of the pairs of input data signals and drives output data signals on first and second output nodes based on the selected pair of input data signals. The hybrid driver includes first and second driver circuits coupled to the first and second output nodes, respectively. Each driver circuit includes first and second series-connected transistors coupled between a first supply voltage node and a reference voltage node, with an interconnection of the first and second series-connected transistors coupled to the corresponding first or second output node. Each first and second driver circuit includes a third transistor coupled in parallel with the corresponding first transistor. Each first and third transistor couples in parallel the corresponding output node to a second supply voltage node responsive to the corresponding low-speed input data signal.
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公开(公告)号：US11075622B1
公开(公告)日：2021-07-27
申请号：US17112172
申请日：2020-12-04
发明人： Thomas Ross , Michael Munroe , James McIntosh
IPC分类号： H03K3/00 , H03K19/0175 , H03K19/0185 , H02M1/08 , H03K17/042
摘要： In one aspect, a gate driver circuit includes a gate driver having a first input connected to a first node and a second input connected to a second node. The gate driver circuit also includes a current source circuit that includes a first transistor and a capacitor having a top plate connected to the source of the first transistor and a bottom plate connected to ground. The gate driver circuit further includes a switch that includes a second transistor. A gate of the second transistor is connected to a drain of the first transistor and a source of the second transistor is connected to the first node.
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