公开(公告)号：US4680752A

公开(公告)日：1987-07-14

申请号：US613392

申请日：1984-05-23

申请人： Tetsuo Takemura ,  Shinobu Gohara

发明人： Tetsuo Takemura ,  Shinobu Gohara

IPC分类号： H04L12/52 ,  H04Q11/06 ,  H04Q11/04

CPC分类号： H04L12/525 ,  H04Q11/06

摘要： A time switch for a time division switch has a function to exchange time slots as well as functions of bit are conversion and multiplexing or demultiplexing. A first stage time switch comprises a channel memory capable of sequential writing and random reading and a converter for converting a data read from the channel memory to a universal signal in accordance with a conversion mode designation. A final stage time switch comprises a channel memory capable of random writing and sequential reading and a control circuit for designating a write bit position of the channel memory in accordance with a write mode designation. An economic time switch having a high flexibility to a traffic variation among bearer signals is provided.

摘要翻译： 用于时分开关的时间开关具有交换时隙的功能，以及位的功能是转换和复用或解复用。 第一级时间开关包括能够进行顺序写入和随机读取的通道存储器，以及用于根据转换模式指定将从通道存储器读取的数据转换为通用信号的转换器。 最后一级时间切换包括能够随机写入和顺序读取的通道存储器和用于根据写入模式指定来指定通道存储器的写入位置的控制电路。 提供了一种对承载信号之间的业务变化具有高灵活性的经济时间切换。

公开(公告)号：US4639910A

公开(公告)日：1987-01-27

申请号：US682228

申请日：1984-12-14

申请人： Herbert J. Toegel ,  Joseph R. Yudichak ,  John F. Gilsdorf

发明人： Herbert J. Toegel ,  Joseph R. Yudichak ,  John F. Gilsdorf

IPC分类号： H04L12/52 ,  H04Q11/04 ,  H04Q1/30

CPC分类号： H04L12/52 ,  H04Q11/0407

摘要： An apparatus for establishing a plurality of communication paths includes a plurality of ports each having different data rates associated therewith and a means for establishing simultaneous paths among the plurality of ports according to instruction signals from terminals interfaced with the ports and carried on the same path as the information to be switched.

摘要翻译： 用于建立多个通信路径的装置包括多个端口，每个端口各自具有与其相关联的不同的数据速率，以及用于根据来自与端口接口的终端的指令信号建立多个端口之间的同时路径的装置， 要切换的信息。

公开(公告)号：US4551831A

公开(公告)日：1985-11-05

申请号：US575581

申请日：1984-01-31

申请人： Mitchell D. Vaughn

发明人： Mitchell D. Vaughn

IPC分类号： H04L12/52 ,  H04Q11/04

CPC分类号： H04Q11/0407 ,  H04L12/52

摘要： A communications network includes a system multiplexer (10) for effecting communication channels between a plurality of peripheral units. The peripheral units include master computers (12), (14) and (16) and various slave devices such as printers (28) and display terminals (26). The multiplexer (10) includes a receive multiplexer (30) and a transmit multiplexer (32) connected together through a communications link (34). The multiplexers are controlled through control logic circuitry (36) which receives signals from a CPU (42). The CPU (42) stores a connection pattern in the control logic circuitry (36) and alters this connection pattern to change the communications link between various peripheral devices. By multiplexing the channels, real time communication is achieved.

摘要翻译： 通信网络包括用于实现多个外围单元之间的通信信道的系统多路复用器（10）。 外围单元包括主计算机（12），（14）和（16）以及各种从设备，例如打印机（28）和显示终端（26）。 多路复用器（10）包括通过通信链路（34）连接在一起的接收多路复用器（30）和发送多路复用器（32）。 多路复用器通过从CPU（42）接收信号的控制逻辑电路（36）来控制。 CPU（42）将连接模式存储在控制逻辑电路（36）中并改变该连接模式以改变各种外围设备之间的通信链路。 通过多路复用通道，实现实时通信。

公开(公告)号：US4530093A

公开(公告)日：1985-07-16

申请号：US510857

申请日：1983-07-05

申请人： Tahir Akram ,  Daniel S. Bartozzi ,  Paul P. Dasiewicz

发明人： Tahir Akram ,  Daniel S. Bartozzi ,  Paul P. Dasiewicz

IPC分类号： H04J3/16 ,  H04L12/52 ,  H04Q11/04 ,  H04J3/02

CPC分类号： H04J3/1647 ,  H04L12/52 ,  H04Q11/04

摘要： A stored program telecommunications system of the hybrid PBX/ey system type. The system uses two level distributed processor architecture for control and switching and pulse code modulation (PCM) for speech transmission. The system controller directs operation of the second level or group controllers, there being one group controller for each group of ports. Ports may be station instruments of either the single line or multiple line type, trunk lines or data terminals. Data from the data terminals is generally slower than the repetition rate of PCM data, therefore system time slots capable of PCM transmission may be allotted to handle more than one data terminal through sub-multiplexing of time slots. The sub-multiplexing of PCM time slots is controlled by the system controller acting through the controller for the group initiating the call with a data interface circuit providing access between a data terminal and a group level speech bus. One data interface circuit may control up to four data terminals.

摘要翻译： 混合PBX / ey系统类型的存储程序电信系统。 该系统使用两级分布式处理器架构进行控制和切换以及用于语音传输的脉码调制（PCM）。 系统控制器指示第二级或组控制器的操作，每个端口组有一个组控制器。 端口可以​​是单线或多线型，中继线或数据终端的站仪表。 来自数据终端的数据通常比PCM数据的重复率慢，因此可以通过时隙的子复用来分配能够进行PCM传输的系统时隙来处理多于一个的数据终端。 PCM时隙的子复用由系统控制器控制，该系统控制器通过控制器发起呼叫，该数据接口电路提供数据终端和组级语音总线之间的接入。 一个数据接口电路可以控制多达四个数据终端。

公开(公告)号：US4512014A

公开(公告)日：1985-04-16

申请号：US175692

申请日：1980-08-06

申请人： Reiner Binz ,  Norbert Pointner

发明人： Reiner Binz ,  Norbert Pointner

IPC分类号： H04J3/24 ,  H04L12/52 ,  H04Q11/04 ,  H04Q11/08 ,  H04J3/02

CPC分类号： H04L12/52 ,  H04Q11/08

摘要： A time slot multiplex device for a time division multiplex system having a voice memory for storing data words received on an input multiplex line, and a control memory for controlling the reading of said voice memory to an output multiplex line, incorporates logic circuitry for generating a plurality of associated pairs of addresses, one for said control memory and one for said voice memory, corresponding to a plurality of equally spaced time slots for a multi-channel connection to said output multiplex line of relatively high band width, in response to a single pair of associated addresses furnished by a higher ranking control means and a logic circuit which, in association with a time slot counter, generates the required addresses during cycling of the time slot counter through a single frame of the time division multiplex system.

摘要翻译： 一种用于时分复用系统的时隙多路复用装置，具有用于存储在输入多路复用线路上接收的数据字的语音存储器和用于控制所述语音存储器到输出多路复用线路的读取的控制存储器，其包括用于产生 多个相关联的地址对，一个用于所述控制存储器，一个用于所述语音存储器，对应于多个相等间隔的时隙，用于响应于单个的相对较高带宽的所述输出多路复用线路的多通道连接 由较高等级控制装置提供的一对关联地址和与时隙计数器相关联的逻辑电路通过时分复用系统的单个帧在时隙计数器的循环期间产生所需的地址。

公开(公告)号：US4430525A

公开(公告)日：1984-02-07

申请号：US338005

申请日：1982-01-08

申请人： Dietmar Franz ,  Norbert Torggler

发明人： Dietmar Franz ,  Norbert Torggler

IPC分类号： H04L12/52 ,  H04L13/08

CPC分类号： H04L12/52

摘要： A data exchange system is connected to at least one signal converter in which digital signals emitted from teletex subscriber stations are converted so that they may be processed by teletex subscriber stations, and vice-versa. In order that the load on the signal converters may be as low as possible in the event that digital signals cannot be deposited in the desired subscriber station, the data exchange system is additionally connected to at least two special teletex transmitting/receiving devices. These teletex transmitting/receiving devices can be operated by a special call signal only in the event that a teletex subscriber station or a signal converter is currently unable to deposit digital signals in the desired subscriber station. In response to such operation of the teletex transmitting/receiving devices, the latter is supplied with digital signals which cannot currently be deposited, together with additional information which enable the establishment of a connection to the desired subscriber station. Subsequently, the teletex transmitting/receiving device is able to transmit the digital signals which it has received, on the basis of the additional information, to the desired subscriber station.

摘要翻译： 数据交换系统连接到至少一个信号转换器，其中从teletex用户站发射的数字信号被转换，使得它们可以被teletex用户站处理，反之亦然。 为了在数字信号不能被存储在期望的用户站中的情况下，信号转换器上的负载可能尽可能低，数据交换系统另外连接到至少两个特殊的电信发送/接收设备。 只有当teletex用户站或信号转换器当前无法在期望的用户站中存储数字信号时，才能通过专用呼叫信号来操作这些teletex发送/接收设备。 响应于电信发送/接收设备的这种操作，后者被提供有无法存储的数字信号以及能够建立到期望用户站的连接的附加信息。 随后，电信发送/接收设备能够根据附加信息将所接收的数字信号发送到期望的用户台。

公开(公告)号：US4412324A

公开(公告)日：1983-10-25

申请号：US264813

申请日：1981-05-18

申请人： Albert Glowinsky ,  Pierre M. Lucas

发明人： Albert Glowinsky ,  Pierre M. Lucas

IPC分类号： H04J3/24 ,  H04L12/52 ,  H04Q11/04 ,  H04J6/00

CPC分类号： H04J3/24 ,  H04L12/52 ,  H04Q11/04

摘要： A bit-by-bit time-division digital switching network switches incoming and outgoing isochronous digital channels having rates which are different but sub-multiples of a given low rate. After phasing the incoming channels, bits having a predetermined binary state are detected. Previously stored addressed words of the outgoing channels to be switched to the incoming channels are read out and multiplexed into an intermediate multiplex highway in response incoming channel bits having the predetermined state. This predetermined state is respectively that of the received bit, or its inverse if the sum of the incoming channel word bits is respectively less than, or greater than half the number of incoming word bits. Each multiplex highway multiframe is composed of a number of outgoing channel address words equal at most to half the number of incoming channels. A frame or certain parts of the multiframe in the multiplex highway indicate, by the presence or the absence of the outgoing channel address word, whether or not the incoming channel word bits have been inverted.

摘要翻译： 逐位时分数字交换网络切换具有不同但给定低速率的子倍数的速率的进入和离开同步数字信道。 在对输入信道进行定相之后，检测到具有预定二进制状态的比特。 对于具有预定状态的输入信道位，先前存储要切换到输入信道的输出信道的存储寻址字被读出并复用到中间多路复用公路。 该预定状态分别是接收到的比特的状态，或者如果进入的信道字比特的和分别小于或者大于输入字比特数的一半，则其为倒数。 每个多路复用公路复帧由等于输入信道数量的一半的多个输出信道地址字组成。 多路复用公路中的帧或多帧的某些部分通过输出信道地址字的存在或不存在来指示输入信道字位是否已被反转。

公开(公告)号：US4144407A

公开(公告)日：1979-03-13

申请号：US846106

申请日：1977-10-27

申请人： Giovanni Zaffignani ,  Carlo Casalino

发明人： Giovanni Zaffignani ,  Carlo Casalino

IPC分类号： H04L12/52 ,  H04J3/06 ,  H04Q3/54

CPC分类号： H04L12/52

摘要： A new, high capacity switching center for telegraphic lines which employs digital elements is herewith described. The system resembles a multiprocessor with hierarchical organization. The general coordinating functions of the system are carried out by a minicomputer having a main memory and a mass memory. Several high speed microcomputers (known as the multiplex subsystem or multiplexer), each having in turn a local working memory, are interconnected to each other and to the minicomputer through a multiplex channel. Telegraphic lines are connected to each microcomputer. These in turn are linked to users in remote locations. The local memories of the microcomputers include an area reserved for the recording of incoming messages from the connected users and an area for recording the outgoing messages to the connected users. The messages received from one of the various microcomputers are sent to the microcomputer linked with the recipient user by employing the time division multiplex technique (TDM). A preselected microcomputer operates as interface between the multiplex subsystems and the minicomputer. All the components of the system (minicomputer and related peripheral units, the interface microcomputer, multiplex subsystem microcomputers, local working memories and communication channels) are duplicated for fail safe reasons. In other words, if any of the switching center components fails, a back up component is automatically substituted thus guaranteeing operational continuity and no loss of messages during the transfer phase.

摘要翻译： 本文介绍了一种采用数字元件的新型高容量电报线路交换中心。 该系统类似于具有分层组织的多处理器。 系统的一般协调功能由具有主存储器和大容量存储器的小型计算机执行。 每个具有本地工作存储器的几个高速微型计算机（称为多路复用子系统或多路复用器）通过多路复用通道彼此互连并连接到小型计算机。 电报线连接到每台微机。 这些又与远程位置的用户相关联。 微型计算机的本地存储器包括保留用于记录来自连接的用户的输入消息的区域和用于将输出消息记录到所连接的用户的区域。 从各种微型计算机之一接收的消息通过采用时分复用技术（TDM）发送到与接收者用户相连的微型计算机。 预选的微型计算机作为多路复用子系统和小型计算机之间的接口。 系统的所有组件（小型计算机及相关外围设备，接口微型计算机，复用子系统微型计算机，本地工作存储器和通信通道）由于出现故障安全的原因而被复制。 换句话说，如果任何交换中心组件出现故障，则自动替换备份组件，从而保证在传输阶段期间的操作连续性和消息的丢失。

公开(公告)号：US4117269A

公开(公告)日：1978-09-26

申请号：US608391

申请日：1975-08-27

申请人： Hans van Kampen

发明人： Hans van Kampen

IPC分类号： H04Q11/04 ,  H04L12/52 ,  H04J3/16

CPC分类号： H04L12/525

摘要： Time division multiplex telecommunication exchange in which each bit group received is compared, in the incoming line circuits, with the preceding bit group. When two successive bit groups are equal, the second group is not supplied to the switching device which serves for the exchange of data between the connected transmission lines. The outgoing line circuits retransmit the bit group when no new bit group is received from the switching device within a predetermined time.

公开(公告)号：US4031314A

公开(公告)日：1977-06-21

申请号：US646538

申请日：1976-01-05

申请人： Hans Bittermann

发明人： Hans Bittermann

IPC分类号： H04L12/52 ,  H04Q3/545 ,  H04Q3/54

CPC分类号： H04L12/52 ,  H04Q3/545

摘要： A circuit arrangement for connection of information transducers, which may be compensating networks in program controlled telecommunication exchange systems is described. In the system the transfer of information between the feeder and consumer lines connected to a line connection unit always occurs over a central memory. The storage areas in the central memory, which are connected to feeder lines, can be reached over input code transducers and contain an address datum identifying the desired outgoing or consumer lines. By means of the address datum, the consumer lines can be reached over output code transducers. Compensating networks are connected at the input end to the outputs of the output code transducer and at the output end to inputs of the input code transducer. Applicable outputs of the output code transducer can be reached over an address datum contained in an associated storage area. Specific storage areas connected to applicable inputs of the input code transducer can be reached over these inputs. These storage areas each contain an address datum identifying the desired consumer line.

摘要翻译： 描述了用于连接信息传感器的电路装置，其可以是程控电信交换系统中的补偿网络。 在系统中，连接到线路连接单元的馈电线和消费线之间的信息传输总是发生在中央存储器上。 连接到馈电线路的中央存储器中的存储区域可以通过输入代码传感器到达，并且包含标识期望的输出或消费者线路的地址数据。 通过地址基准，消费者线路可以通过输出代码传感器达到。 补偿网络在输入端连接到输出代码传感器的输出端，输出端连接到输入代码传感器的输入端。 可以通过包含在相关联的存储区域中的地址数据来达到输出代码变换器的适用输出。 连接到输入代码传感器的适用输入的特定存储区可以通过这些输入来达到。 这些存储区域各自包含标识所需消费者线路的地址数据。