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    Switch for serial or parallel communication networks
    6.
    发明授权
    Switch for serial or parallel communication networks 失效
    切换串行或并行通信网络

    公开(公告)号：US5331315A

    公开(公告)日：1994-07-19

    申请号：US898081

    申请日：1992-06-12

    申请人： Dario B. Crosette

    发明人： Dario B. Crosette

    IPC分类号： G06F15/173 ,  H04Q3/54 ,  G06F13/362 ,  H04J3/16 ,  H04Q11/06

    CPC分类号： G06F15/17375 ,  G06F15/17343

    摘要： A communication switch apparatus and a method for use in a geographically extensive serial, parallel or hybrid communication network linking a multi-processor or parallel processing system has a very low software processing overhead in order to accommodate random burst of high density data. Associated with each processor is a communication switch. A data source and a data destination, a sensor suite or robot for example, may also be associated with a switch. The configuration of the switches in the network are coordinated through a master processor node and depends on the operational phase of the multi-processor network: data acquisition, data processing, and data exchange. The master processor node passes information on the state to be assumed by each switch to the processor node associated with the switch. The processor node then operates a series of multi-state switches internal to each communication switch. The communication switch does not parse and interpret communication protocol and message routing information. During a data acquisition phase, the communication switch couples sensors producing data to the processor node associated with the switch, to a downlink destination on the communications network, or to both. It also may couple an uplink data source to its processor node. During the data exchange phase, the switch couples its processor node or an uplink data source to a downlink destination (which may include a processor node or a robot), or couples an uplink source to its processor node and its processor node to a downlink destination.

    摘要翻译： 在多处理器或并行处理系统的地理上广泛的串行，并行或混合通信网络中使用的通信交换装置和方法具有非常低的软件处理开销以便适应高密度数据的随机突发。 与每个处理器相关联的是一个通讯开关。 例如，数据源和数据目的地，传感器套件或机器人也可以与开关相关联。 网络中的交换机的配置通过主处理器节点协调，并且取决于多处理器网络的操作阶段：数据采集，数据处理和数据交换。 主处理器节点将关于每个交换机假设的状态的信息传递给与交换机相关联的处理器节点。 然后，处理器节点在每个通信交换机内部操作一系列多状态交换机。 通信交换机不解析和解释通信协议和消息路由信息。 在数据采集阶段期间，通信交换机将产生数据的传感器与与交换机相关联的处理器节点耦合到通信网络上的下行链路目的地，或耦合到两者。 它也可以将上行链路数据源耦合到其处理器节点。 在数据交换阶段期间，交换机将其处理器节点或上行链路数据源耦合到下行链路目的地（其可以包括处理器节点或机器人），或将上行链路源耦合到其处理器节点及其处理器节点到下行链路目的地 。

    Apparatus for loading memories in a telecommunication exchange
    8.
    发明授权
    Apparatus for loading memories in a telecommunication exchange 失效
    用于在电信交换机中装载存储器的装置

    公开(公告)号：US4556971A

    公开(公告)日：1985-12-03

    申请号：US525033

    申请日：1983-08-08

    申请人： Thomas Thyni

    发明人： Thomas Thyni

    IPC分类号： H04Q3/60 ,  H04M3/22 ,  H04Q20060101 ,  H04Q3/54 ,  H04Q3/545 ,  H04Q11/04

    CPC分类号： H04Q3/54516

    摘要： An apparatus is provided for charging memories in a telecommunication exchange which includes line modules (LIM). These have communication paths for communication with terminals and possibly external apparatus, and have a control computer (LPU) for maintaining communication between terminals or between a terminal and external apparatus. The communication between terminals connected to different modules is set up via a digital group selector. To enable writing from a data information source (BS, TS) to all the module control computers in a single process through a module (LIM 1) selected as a main unit, the data information to be written is preceded by conditioning information (INP 1, INP 2, etc). This actuates a loading means (UPK) for establishing a connection to an addressed module (LIM 1-LIM 32) with the aid of initial information written into an unchangeable memory (MIN) in the module. Furthermore, it adjusts a decoding means (AVK) in correspondence with an identity number assigned to the module until all modules are conditioned and connected to the data information source via a common communication path. Each of the modules can only take the data information for which its decoding means is adjusted. A terminal signal in the data information disconnects all the modules connected to the common communication path.

    摘要翻译： PCT No.PCT / SE82 / 00417 Sec。 371日期：1983年8月8日 102（e）日期1983年8月8日PCT提交1982年12月7日PCT公布。 公开号WO83 / 02209 日期：1983年6月23日。提供一种用于在包括线路模块（LIM）的电信交换机中为存储器充电的装置。 它们具有用于与终端和可能的外部设备通信的通信路径，并且具有用于维持终端之间或终端与外部设备之间的通信的控制计算机（LPU）。 连接到不同模块的终端之间的通信通过数字组选择器建立。 为了允许通过选择为主单元的模块（LIM 1）从单个进程中将数据信息源（BS，TS）写入所有模块控制计算机，要写入的数据信息之前是调节信息（INP 1 ，INP 2等）。 借助于写入模块中不可更改的存储器（MIN）的初始信息，这将启动加载装置（UPK），用于建立与寻址模块（LIM 1-LIM 32）的连接。 此外，它调整与分配给模块的身份号对应的解码装置（AVK），直到所有模块经过公共通信路径被调节并连接到数据信息源。 每个模块只能取得调整其解码装置的数据信息。 数据信息中的终端信号断开连接到公共通信路径的所有模块。

    Arrangement of interactive processors for control of ports
    9.
    发明授权
    Arrangement of interactive processors for control of ports 失效
    用于控制端口的交互式处理器的布置

    公开(公告)号：US4479034A

    公开(公告)日：1984-10-23

    申请号：US507935

    申请日：1983-06-23

    申请人： Barrie Brightman ,  Thomas E. Ellis ,  James E. Jones ,  Pedro A. Lenk ,  William H. Stewart ,  John W. Woodward

    发明人： Barrie Brightman ,  Thomas E. Ellis ,  James E. Jones ,  Pedro A. Lenk ,  William H. Stewart ,  John W. Woodward

    IPC分类号： H04M19/02 ,  H04Q11/04 ,  H04M3/02 ,  H04Q3/54

    CPC分类号： H04M19/026 ,  H04Q11/0407

    摘要： A common control for a community office (C.O.) switching system includes two interactive processors. One of these interactive processors is a call control processor which comprises the uppermost element in the control hierarchy. It is a stored program processor and its functions include: (i) control of call progression, (ii) marking paths through the matrix switch network, and translations. The other of these interactive processors is a port event processor. It is a construction of electronic logic circuitry known as "combinatorial logic". The port event processor operates on the principle of the combinatorial logic being sequentially coupled to every one of the port equipment positions over a 4 millisecond scan cycle. A pair of functional units of the port event processor provide the common control capability to sense or transmit supervisory events. These function units also interact with the call control processor in a way which permits the latter to function as the uppermost hierarchical element of the common control with substantially no burden of performing real-time tasks connected with port events. The interaction between the call control processor and the port event processor is effected through a port data store which provides an individual port data field per port equipment position. In general, each port data field is accessible to either of the interactive processors.

    摘要翻译： 社区办公室（C.O.）切换系统的共同控制包括两个交互式处理器。 这些交互式处理器之一是呼叫控制处理器，其包括控制层级中的最上面的元素。 它是一个存储的程序处理器，其功能包括：（i）控制呼叫进程，（ii）通过矩阵切换网络标记路径和翻译。 这些交互式处理器中的另一个是端口事件处理器。 它是一种称为“组合逻辑”的电子逻辑电路的结构。 端口事件处理器的操作原理是组合逻辑在4毫秒的扫描周期上顺序耦合到每个端口设备位置。 端口事件处理器的一对功能单元提供用于感测或发送监督事件的共同控制能力。 这些功能单元还可以以这种方式与呼叫控制处理器进行交互，这种方式使得后者可以充当公共控制的最上层的分层元件，基本上没有执行与端口事件相关的实时任务的负担。 呼叫控制处理器和端口事件处理器之间的交互通过端口数据存储来实现，该端口数据存储器为端口设备位置提供单独的端口数据字段。 通常，每个端口数据字段都可以被任何一个交互式处理器访问。

    Dual tone multifrequency and dial pulse receiver
    10.
    发明授权
    Dual tone multifrequency and dial pulse receiver 失效
    双音多频和拨号脉冲接收机

    公开(公告)号：US4460806A

    公开(公告)日：1984-07-17

    申请号：US377574

    申请日：1982-05-13

    申请人： Ronald J. Canniff ,  Gordon K. Lin

    发明人： Ronald J. Canniff ,  Gordon K. Lin

    IPC分类号： H04L27/26 ,  H04Q1/32 ,  H04Q1/457 ,  H04J3/12 ,  H04Q3/54

    CPC分类号： H04Q1/32 ,  H04Q1/4575

    摘要： A dual tone multifrequency and dial pulse receiver that receives 8000 digital data words per second, each of the data words including eight PCM bits representing the analog signal transmitted from a subscriber set and also including a line status bit indicating the DC status of the line. The receiver includes a time-shared processor which processes the PCM bits of 4000 words per second to detect tone-pairs and which also processes the line status bit of 4000 words per second to detect valid dial pulse sequences. The time-shared processor stores one of a first plurality of code words in a register when a tone-pair is detected and stores one of a second plurality of code words in the register when a valid dial pulse sequence is detected. Advantageously, the receiver can detect either dual tone multifrequency or dial pulse signaling from a subscriber even though the type of signaling to be used by the subscriber is not known a priori.

    摘要翻译： 双音多频和拨号脉冲接收机，每秒接收8000个数字数据字，每个数据字包括表示从订户集发送的模拟信号的八个PCM位，并且还包括指示行的直流状态的行状态位。 该接收机包括一个时间共享处理器，处理每秒4000个字的PCM位以检测音调对，并且还处理每秒4000个字的线路状态位以检测有效拨号脉冲序列。 当检测到音调对时，时间共享处理器将第一多个码字中的一个存储在寄存器中，并且当检测到有效的拨号脉冲序列时，将第二多个码字中的一个存储在寄存器中。 有利的是，接收机可以检测来自订户的双音多频或拨号脉冲信令，即使用户使用的信令的类型不是先验已知的。