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公开(公告)号：US20220367334A1
公开(公告)日：2022-11-17
申请号：US17737903
申请日：2022-05-05
发明人： Wen-Hsien HUANG , Kwok Cheung TSANG
IPC分类号： H01L23/498 , H01L23/00 , H01L21/48
摘要： One or more implementations of the subject technology may enable a bond-on-pad (BoP) substrate technology that can eliminate the need to utilize a solder-on-pad (SoP) process. Unlike an SoP process, a BoP Process does not require a solder bump to be formed on a bump pad to attach a joint to a bump pad. The size of an opening on a bump pad for a BoP process may be larger than that of an SoP process. A BoP process may use a solder mask having multiple thicknesses and may be thinner near the bump pads. A BoP process may use a joint having a copper pillar and a solder cap. A BoP process can be used with an underfill or a molding compound technology.
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公开(公告)号：US20220358896A1
公开(公告)日：2022-11-10
申请号：US17869734
申请日：2022-07-20
摘要： A system and method are provided to generate blended video and graphics using a blending domain. The system converts video from a first domain to a blending domain. The system converts graphics from a second domain to the blending domain and blends the video and graphics in the blending domain to generate a blended output.
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公开(公告)号：US20220321504A1
公开(公告)日：2022-10-06
申请号：US17845854
申请日：2022-06-21
IPC分类号： H04L49/505 , H04L49/90
摘要： The disclosed systems and methods provide methods and systems for providing power throttling adapted for high performance network switches. A method includes determining, for each of a plurality of measurement periods within a thermal average period, an energy usage estimate for a packet processing block configured to process ingress packets at a power gated clock rate. The method includes determining, for each of the plurality of measurement periods, a target clock rate for the packet processing block based on the determined energy usage estimates to meet a target energy value that is averaged for the thermal average period. The method includes adjusting, for each of the plurality of measurement periods, the power gated clock rate towards the target clock rate, wherein the adjusting causes the packet processing block to process the ingress packets at the adjusted power gated clock rate.
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公开(公告)号：US11451283B2
公开(公告)日：2022-09-20
申请号：US17306826
申请日：2021-05-03
发明人： Roy Oren , Daniel Stopler , Shimon Benjo
IPC分类号： H04B7/06
摘要： A method for channel smoothing with transmit beamforming includes transmitting, by a first device, a non-data-packet (NDP) frame to a second device. The method also includes receiving, by the second device, the NDP frame and transmitting a compressed report to the first device. The method further includes receiving, by the first device, the compressed report and deriving a first beamforming matrix from the compressed report. A second beamforming matrix is generated employing a processing known to the second device, and a data frame is transmitted to the second device using the second beamforming matrix.
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公开(公告)号：US20220295125A1
公开(公告)日：2022-09-15
申请号：US17826862
申请日：2022-05-27
IPC分类号： H04N21/234 , H04N21/2343 , H04N21/2387 , H04N21/462 , H04N21/472
摘要： Systems, methods and apparatuses for handling trick mode operation using multiple video streams are provided. A media server presents a first video stream having a first level of a video characteristic for display. The media server, in response to receiving a first command, presents a second video stream having a second level of the video characteristic for display while stopping presenting the first video stream for display based on a determination determined using the first level of the video characteristic and the second level of the video characteristic. The first video stream and the second video stream are directed to the same video content.
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公开(公告)号：US11438219B2
公开(公告)日：2022-09-06
申请号：US17175537
申请日：2021-02-12
IPC分类号： H04L41/0677 , H04L12/46 , H04L45/02 , H04L45/586 , H04L49/55 , H04L49/00
摘要： One embodiment of the present invention provides a switch system. The switch includes a port that couples to a server hosting a number of virtual machines. The switch also includes a link tracking module. During operation, the link tracking module determines that reachability to at least one end host coupled to a virtual cluster switch of which the switch is a member is disrupted. The link tracking module then determines that at least one virtual machine coupled to the port is affected by the disrupted reachability, and communicates to the server hosting the affected virtual machine about the disrupted reachability.
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77.发明授权公开(公告)号：US11426660B2
公开(公告)日：2022-08-30
申请号：US16730166
申请日：2019-12-30
发明人： Ahmadreza (Reza) Rofougaran , Maryam Rofougaran , Nambirajan Seshadri , Brima B. Ibrahim , John Walley , Jeyhan Karaoguz
IPC分类号： A63F13/573 , A63F13/211 , A63F13/213 , A63F13/235 , A63F13/212 , G01S7/41 , G01S13/87 , G06F3/01 , G06F3/0346 , G01S13/42 , G01S7/42 , A63F13/57 , A63F13/825 , G06F3/045
摘要： A gaming object includes an orientation sensor that generates orientation data in response to the orientation of the gaming object. An actuator that generates interaction data in response to an action of a user. A transceiver sends an RF signal to a game device that indicates the orientation data and the interaction data. The game device generates display data for display on a display device that contains at least one interactive item, and wherein the at least one interactive item is interactive in response to the orientation data and the interaction data.
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公开(公告)号：US20220239257A1
公开(公告)日：2022-07-28
申请号：US17160293
申请日：2021-01-27
发明人： Sean Thomas HANSEN , Jeesu KIM
摘要： A filter device configured to directly connect to a differential power amplifier of a transmit chain circuit. The filter device may include a transformer and a filter configured as a half lattice equivalent topology and having a single-ended output. The filter may be a lattice filter configured as a full lattice topology or a lattice equivalent filter configured as a half lattice equivalent topology. The filter includes a first branch having a first impedance network of one or more first impedance elements and a second branch having a second impedance network of one or more second impedance elements. The single-ended output of the filter device may connect to an antenna switch that is in turn connected to an antenna.
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公开(公告)号：US20220210424A1
公开(公告)日：2022-06-30
申请号：US17696740
申请日：2022-03-16
发明人： Minhua ZHOU
IPC分类号： H04N19/13 , H04N19/119 , H04N19/126 , H04N19/91 , H04N19/52 , H04N19/61 , H04N19/159
摘要： In the subject architecture flexible binary arithmetic coding system, coding circuitry of an electronic device may receive video data that is to be coded (e.g., to be encoded or decoded) by binary arithmetic coding. The coding circuitry may also compute at least one of a least probable symbol (LPS) range or a most probable symbol (VIPS) range based on a multiplication operation (e.g., without performing a table look-up operation). The coding circuitry may perform binary arithmetic coding on the video data using the at least one of the LPS range or the MPS range. The computation of the LPS range and/or the MPS range using the multiplication operation may have a lower computational cost than using a table look-up operation.
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公开(公告)号：US11368412B2
公开(公告)日：2022-06-21
申请号：US16945562
申请日：2020-07-31
IPC分类号： H04L49/505 , H04L49/90
摘要： The disclosed systems and methods provide methods and systems for providing power throttling adapted for high performance network switches. A method includes determining, for each of a plurality of measurement periods within a thermal average period, an energy usage estimate for a packet processing block configured to process ingress packets at a power gated clock rate. The method includes determining, for each of the plurality of measurement periods, a target clock rate for the packet processing block based on the determined energy usage estimates to meet a target energy value that is averaged for the thermal average period. The method includes adjusting, for each of the plurality of measurement periods, the power gated clock rate towards the target clock rate, wherein the adjusting causes the packet processing block to process the ingress packets at the adjusted power gated clock rate.
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