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公开(公告)号：US11830763B2
公开(公告)日：2023-11-28
申请号：US17278855
申请日：2020-07-24
Inventor： Shan Zhang , Lianjie Qu , Yonglian Qi , Hebin Zhao
IPC: H01L21/765 , H01L21/762 , H01L21/683 , H01L27/12 , H01L29/66 , H01L29/786 , G06V40/13
CPC classification number: H01L21/76254 , H01L21/6835 , H01L27/127 , H01L29/66772 , H01L29/78654 , G06V40/1318 , H01L2221/68368
Abstract: A method of manufacturing thin film transistor(s) includes: providing a monocrystalline silicon wafer, the monocrystalline silicon wafer including a first surface and a second surface that are opposite to each other; forming a bubble layer between the first surface and the second surface of the monocrystalline silicon wafer, the bubble layer dividing the monocrystalline silicon wafer into two portions arranged side by side in a direction perpendicular to the second surface, and a portion of the monocrystalline silicon wafer that is located between the bubble layer and the second surface being a monocrystalline silicon film having a target thickness; providing a substrate, and transferring the monocrystalline silicon film onto the substrate by breaking the monocrystalline silicon wafer at the bubble layer; and patterning the monocrystalline silicon film transferred to the substrate to form active layer(s) of the thin film transistor(s).
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公开(公告)号：US11830398B2
公开(公告)日：2023-11-28
申请号：US17434987
申请日：2020-12-28
Inventor： Yan Yan , Yu Ma , Weitao Chen , Xiaopeng Cui
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2300/0842 , G09G2310/0267 , G09G2310/0286
Abstract: A shift register circuit includes a first pull-down control sub-circuit and a first noise reduction sub-circuit. The first pull-down control sub-circuit includes a first transistor and a second transistor, and a ratio of a width-to-length ratio of a channel of the second transistor to a width-to-length ratio of a channel of the first transistor is greater than 5:1. The first pull-down control sub-circuit transmits, in response to a first voltage signal received at a first voltage signal terminal, the first voltage signal to a first pull-down node through the first transistor, and transmits a second voltage signal received at a second voltage signal terminal to the first pull-down node through the second transistor under control of a voltage of a pull-up node. The first noise reduction sub-circuit transmits the second voltage signal to the pull-up node under control of a voltage of the first pull-down node.
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公开(公告)号：US20230377506A1
公开(公告)日：2023-11-23
申请号：US17634733
申请日：2021-03-29
Inventor： Qiujie SU , Yingmeng MIAO , Dongchuan CHEN , Yanping LIAO , Seungmin LEE , Xibin SHAO , Xiaofeng YIN
CPC classification number: G09G3/2096 , G06F3/0412 , G06F3/0416 , G09G2310/0267 , G09G2310/0275
Abstract: A display module and a display apparatus, relate to the technical filed of display. At least one chip group and a group of first PLG wirings corresponding to each of the chip groups are disposed in a first bonding area, each of the chip groups includes at least two groups of chip units, each group of the chip units includes at least one gate drive chip, each group of the first PLG wirings includes a first wiring and at least one second wiring; power pins of any two adjacent gate drive chips are connected by the first wiring, each of the second wirings surrounds and passes through each of the gate drive chips, the first wirings connected with the power pin of the last gate drive chip in the previous group of the chip units and any of the second wirings, are parallelly connected with the power pin of the first gate drive chip in the next group of the chip units, to reduce the luminance difference of pixels driven by the gate drive chips in each group of the chip units.
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公开(公告)号：US20230360615A1
公开(公告)日：2023-11-09
申请号：US17633008
申请日：2021-04-09
Inventor： Dongchuan CHEN , Yanping LIAO , Yingmeng MIAO , Yinlong ZHANG , Shulin YAO , Xibin SHAO , Seungmin LEE , Jiantao LIU
IPC: G09G3/36
CPC classification number: G09G3/3614 , G09G2310/08 , G09G2310/0213 , G09G2310/0251 , G09G2310/0205 , G09G2320/0257 , G09G2340/0435
Abstract: A display driving method, a display driving device and a display device are provided. The display driving method includes: when displaying an odd-numbered frame, providing first parity row data of the odd-numbered frame to a display array, to enable a third parity row of the display array to be displayed based on real data of the first parity row data and enable a fourth parity row of the display array to be displayed based on interpolation data of the first parity row data; and when displaying an even-numbered frame, providing second parity row data of the even-numbered frame to the display array, to enable the fourth parity row of the display array to be displayed based on real data of the second parity row data and enable the third parity row of the display array to be displayed based on interpolation data of the second parity row data.
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公开(公告)号：US20230359090A1
公开(公告)日：2023-11-09
申请号：US17312306
申请日：2020-12-30
Inventor： Chunguang TIAN , Tianyu XIA , Xiaolong LI
IPC: G02F1/1343 , G02F1/1333 , G02F1/1362
CPC classification number: G02F1/134309 , G02F1/133345 , G02F1/136286
Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a display region and a peripheral region surrounding the display region, and includes: a common electrode line extending in a first direction on a base substrate and arranged at the display region and the peripheral region; a first conductive pattern arranged at the peripheral region and electrically connected to the common electrode line; an insulation layer covering the first conductive pattern and the common electrode line, a via-hole being formed in the insulation layer, an orthogonal projection of the via-hole onto the base substrate not overlapping an orthogonal projection of the common electrode line onto the base substrate; and a second conductive pattern arranged at the peripheral region and at a side of the insulation layer distal to the first conductive pattern, and electrically connected to the first conductive pattern through the via-hole.
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Patent Agency Ranking
公开(公告)号：US11804196B2
公开(公告)日：2023-10-31
申请号：US17429919
申请日：2020-10-23
Inventor： Tengfei Ding , Yang Wang , Shijun Wang , Bo Feng , Jun Fan , Wenkai Mu , Yi Liu , Xinlan Yang , Li Tian
IPC: G09G3/36 , G02F1/1362
CPC classification number: G09G3/3674 , G09G3/3677 , G02F1/1362 , G09G2300/0408 , G09G2300/0426 , G09G2300/0452 , G09G2310/0202 , G09G2310/0286 , G09G2310/08 , G09G2330/023
Abstract: Provided is a display substrate. The display substrate includes a base substrate, a plurality of gate lines, a plurality of data lines, and a plurality of rows of pixels arranged in an array on the base substrate, and a plurality of shift circuits disposed on the base substrate, wherein in a plurality of pixels connected to each shift circuit, the respective pixels sharing the same data line have the same color, and each shift circuit is connected to one turn-on signal terminal.
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公开(公告)号：US20230333425A1
公开(公告)日：2023-10-19
申请号：US18211008
申请日：2023-06-16
Inventor： Xibin SHAO , Xiaona LIU , Rui ZHANG
IPC: G02F1/1335 , G02F1/1339 , G02F1/1343
CPC classification number: G02F1/133514 , G02F1/1339 , G02F1/134336
Abstract: A display panel and a display apparatus. The display panel includes an array substrate and a color filter substrate opposite to each other, the array substrate being provided with a plurality of pixel regions arranged in an array, and the pixel regions closest to corners of the array substrate being first-type pixel regions, where the color filter substrate includes: a base substrate; a sealant between the base substrate and the array substrate; and a color filter layer on the base substrate and including a plurality of filter units, where the filter units includes first filter units corresponding to the first-type pixel regions, a portion of an orthographic projection of the first filter unit onto the base substrate facing a corner of the base substrate has a non-right-angle contour, and orthographic projections of the first filter unit and the sealant onto the base substrate do not overlap with each other.
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公开(公告)号：US11789301B2
公开(公告)日：2023-10-17
申请号：US17044193
申请日：2019-09-04
Inventor： Jixing Sun , Xinrui Wang , Xiaoyang Guan
IPC: G02F1/1333 , F21V8/00
CPC classification number: G02F1/133342 , G02B6/005 , G02B6/0021 , G02B6/0063 , G02B6/0088 , G02B6/0091 , G02F1/133308 , G02F1/13332 , G02F1/133314 , G02F1/133317 , G02F1/133322
Abstract: A light guide plate includes: a light guide plate body having two light-exit surfaces that are opposite and parallel, and at least one light-incident surface that intersects the two light-exit surfaces; and a mounting portion located on a non-light-incident side of the light guide plate body. The mounting portion and the light guide plate body are an integrated structure, and a portion of the mounting portion located on a light-exit side of each light-exit surface of the two light-exit surfaces is configured to mount an optical film group and a display panel.
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公开(公告)号：US11783744B2
公开(公告)日：2023-10-10
申请号：US17445810
申请日：2021-08-24
Inventor： Qiujie Su , Zhihua Sun , Yingmeng Miao , Yinlong Zhang , Feng Qu , Seungmin Lee , Yanping Liao , Xibin Shao
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2310/0286 , G09G2310/08
Abstract: A gate driving circuit, a method for driving the gate driving circuit, and a display panel. The gate driving circuit includes N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where N, k and K are positive integers, and 1≤k≤K≤N; and an input signal terminal of a n-th stage of shift register is connected to an output signal terminal of a (n−i)-th stage of shift register, and reset signal terminals of the n-th and (n+1)-th stages of shift registers are connected to an output signal terminal of a (n+j)-th stage of shift register, wherein the n is one of an odd number and an even number, where i and j are positive integers, 1
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公开(公告)号：US11774797B2
公开(公告)日：2023-10-03
申请号：US17620321
申请日：2021-02-04
Inventor： Guangyun Tong , Shixin Geng , Lijin Zhao , Tengfei Wang , Jiangfeng Zhang , Xu Chen , Zhuolong Li , Yu Zhang
IPC: G02F1/13357 , G02F1/1335
CPC classification number: G02F1/133603 , G02F1/133612
Abstract: A backlight source includes light bars, adapter plate(s) and connection structures. Each light bar includes light-emitting group(s) and external connection unit(s). Each external connection unit is electrically connected to at least one light-emitting group and included at least one first electrode pair. Each adapter plate includes adapter circuits, each adapter circuit includes adapter units, each adapter unit includes at least one second electrode pair. Ends of each connection structure are electrically connected to one external connection unit and one adapter unit. All second electrode pairs of adapter units of a same adapter circuit are classified into at least one group, each group includes second electrode pairs electrically connected in series. In light-emitting groups electrically connected to adapter units of the same adapter circuit, light-emitting groups electrically connected second electrode pairs in a same group are connected in series to form a dimming region.
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