公开(公告)号：US20120241774A1

公开(公告)日：2012-09-27

申请号：US13367847

申请日：2012-02-07

Applicant: Shih-Hsiang Chen ,  Chih-Jen Chang

Inventor： Shih-Hsiang Chen ,  Chih-Jen Chang

IPC: H01L27/15 ,  H01L33/50

CPC classification number: G02F1/133308 ,  G02F2001/133325

Abstract: A display module and a manufacturing method thereof are provided. The display module comprises a casing, an optical element and a display panel. The casing has an upper portion. The optical element is disposed in the casing. The display panel comprises a color filter substrate and a thin film transistor substrate. The color filter substrate is located within and toward the casing. The thin film transistor substrate is connected to the color filter substrate and connected to the upper portion of the casing.

Abstract translation: 提供了显示模块及其制造方法。 显示模块包括壳体，光学元件和显示面板。 壳体具有上部。 光学元件设置在壳体中。 显示面板包括滤色器基板和薄膜晶体管基板。 滤色器基板位于壳体内并朝向壳体。 薄膜晶体管基板连接到滤色器基板并连接到壳体的上部。

公开(公告)号：US20120204190A1

公开(公告)日：2012-08-09

申请号：US13365778

申请日：2012-02-03

Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

IPC: G06F9/46

CPC classification number: G06F9/546 ,  G06F9/544

Abstract: A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.

Abstract translation: 提供了一种机制，用于在来自解析器的网络处理器结果和来自提供由所述解析器请求的处理支持的外部协处理器的结果中合并。 结果队列中的机制排队，解析器结果需要与协处理器结果合并，并且不需要与协处理器结果合并的解析器结果。 使用一个附加队列来排列存储解析器结果的结果队列的地址。 协处理器的结果是在简单的响应寄存器中接收的。 协处理器结果由响应寄存器的结果队列管理逻辑读取，并被合并到在附加队列中排队的地址的结果队列中读取的相应的不完整解析器结果。

公开(公告)号：US20120192190A1

公开(公告)日：2012-07-26

申请号：US13011663

申请日：2011-01-21

Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

IPC: G06F9/46

CPC classification number: G06F15/1735

Abstract: A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode. The method comprises operatively coupling an Ethernet adapter to a multi-core processor system via a processor bus, selectively assigning a first plurality of packets to a first queue pair for servicing in an endpoint mode, running a device driver on the multi-core processing system, the device driver controlling the servicing of the first queue pair by dispatching the first plurality of packets to only one processor core of the multi-core processor system, selectively assigning a second plurality of packets to a second queue pair for servicing in a network node mode; and the Ethernet adapter controlling the servicing of the second queue pair by dispatching the second plurality of packets to multiple processor threads.

Abstract translation: 提供主机以太网适配器（HEA）和管理网络通信的方法。 HEA包括被配置为通过处理器总线与多核处理器进行通信的主机接口。 所述主机接口包括接收处理元件，所述接收处理元件包括接收处理器，接收缓冲器和用于从所述接收缓冲器向所述接收处理器分发分组的调度器; 包括发送处理器和发送缓冲器的发送处理元件; 以及用于从完成队列（CQ）的头部将网络节点模式中的多核处理器的线程调度完成队列元素（CQE）的完成队列调度器（CQS）。 该方法包括经由处理器总线可操作地将以太网适配器耦合到多核处理器系统，选择性地将第一多个分组分配到第一队列对以在端点模式下进行服务，在多核处理系统上运行设备驱动程序 所述设备驱动程序通过将所述第一多个分组分派到所述多核处理器系统的一个处理器核心来控制所述第一队列对的服务，选择性地将第二多个分组分配给第二队列对以在网络节点中进行服务 模式; 以及所述以太网适配器通过将所述第二多个分组分派到多个处理器线程来控制所述第二队列对的服务。

公开(公告)号：US07995472B2

公开(公告)日：2011-08-09

申请号：US12348938

申请日：2009-01-06

Applicant: Jean L. Calvignac ,  Chih-jen Chang ,  Joseph F. Logan ,  Fabrice J. Verplanken ,  Daniel Wind

Inventor： Jean L. Calvignac ,  Chih-jen Chang ,  Joseph F. Logan ,  Fabrice J. Verplanken ,  Daniel Wind

IPC: G01R31/08 ,  H04L12/28 ,  H04L12/54

CPC classification number: H04L47/527 ,  H04L47/50 ,  H04L47/522 ,  H04L47/568 ,  H04L47/58

Abstract: A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.

Abstract translation: 提供了一种用于灵活数据流的网络处理器数据流芯片和方法。 数据流芯片包括多个片上数据传输和调度电路结构。 响应于指标选择数据传输和调度电路结构。 数据传输电路结构可以包括可选择的帧处理和数据传输功能。 可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。 调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。 在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。

公开(公告)号：US20110158254A1

公开(公告)日：2011-06-30

申请号：US12650174

申请日：2009-12-30

Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Colin Beaton Verrilli

Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Colin Beaton Verrilli

IPC: H04J3/22

CPC classification number: H04L47/522 ,  H04L47/6215

Abstract: A method and apparatus for assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. In a given processing period, a source is selected in a manner that maintains fairness in the selection process. A corresponding sink is selected for the selected source based on processing efficiency. If, due to assignment constraints, no sink is available for the selected source, the selected source is retained for selection in the next scheduling period, to maintain fairness. In this case, to optimize efficiency, a most efficient currently available sink is identified and a source for providing work to that sink is selected.

Abstract translation: 一种用于从多个源（例如网络处理设备中的数据队列）将诸如数据分组的工作分配给诸如网络处理设备中的处理器线程的多个接收器的方法和装置。 在给定的处理期间，以选择过程中保持公平的方式选择源。 基于处理效率为所选择的源选择相应的接收器。 如果由于分配限制，所选择的源没有可用的接收器，所选择的源被保留用于在下一个调度周期中进行选择，以保持公平性。 在这种情况下，为了优化效率，识别出最有效的当前可用的接收器，并且选择用于向该接收器提供工作的源。

公开(公告)号：US20110158250A1

公开(公告)日：2011-06-30

申请号：US12650120

申请日：2009-12-30

Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Terry L. Nelms, II ,  Fabrice Jean Verplanken

Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Terry L. Nelms, II ,  Fabrice Jean Verplanken

IPC: H04L12/56

CPC classification number: H04L49/9047

Abstract: A method and apparatus for assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. In a given processing period, sinks that are available to receive work are identified and sources qualified to send work to the available sinks are determined taking into account any assignment constraints. A single source is selected from an overlap of the qualified sources and sources having work available. This selection may be made using a hierarchical source scheduler for processing subsets of supported sources simultaneously in parallel. A sink to which work from the selected source may be assigned is selected from available sinks qualified to receive work from the selected source.

Abstract translation: 一种用于从多个源（例如网络处理设备中的数据队列）将诸如数据分组的工作分配给诸如网络处理设备中的处理器线程的多个接收器的方法和装置。 在给定的处理期间，确定可用于接收工作的接收器，并且考虑到任何分配约束来确定用于将工作发送到可用接收器的资源。 从具有可用工作的合格来源和源的重叠中选择单个来源。 可以使用用于并行同时处理所支持的源的子集的分级源调度器来进行该选择。 从可选择的来源可以分配工作的接收端从有资格从所选源接收工作的可用接收器中选择。

公开(公告)号：US07715428B2

公开(公告)日：2010-05-11

申请号：US11669419

申请日：2007-01-31

Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Herman D. Dierks, Jr. ,  Christoph Raisch ,  Jan-Bernd Themann ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Herman D. Dierks, Jr. ,  Christoph Raisch ,  Jan-Bernd Themann ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

IPC: H04L12/66 ,  H04J3/16 ,  H04J3/22

CPC classification number: H04L47/50

Abstract: Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.

Abstract translation: 提供了用于处理数据处理设备之间的通信的机制。 利用说明性实施例的机制，提供了一组通过在多个处理核上分发发送和接收侧处理来维持媒体速度的技术。 此外，这些技术还可以设计出多线程网络接口控制器（NIC）硬件，可有效地隐藏通过输入/输出（I / O）总线传输数据分组的直接存储器访问（DMA）操作的延迟。 多个处理核心可以使用通信协议栈和设备驱动程序的单独实例同时运行，以处理用于传输的数据分组，其中单独的硬件实现了处理这些数据分组以进行传输的网络适配器中的发送队列管理器。 可以使用网络适配器中的多个硬件接收分组处理器以及流分类引擎将接收到的数据分组路由到适当的接收队列和处理核心进行处理。

公开(公告)号：US07466715B2

公开(公告)日：2008-12-16

申请号：US11091245

申请日：2005-03-28

Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Joseph F. Logan ,  Fabrice J. Verplanken

Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Joseph F. Logan ,  Fabrice J. Verplanken

IPC: H04L12/28

CPC classification number: H04L12/5601 ,  H04L49/90 ,  H04L2012/5642 ,  H04L2012/5652 ,  H04L2012/5658 ,  H04L2012/5681

Abstract: A communication network used to link information handling systems together utilizes a switching network to transmit data among senders and receivers. Each individual packet of data is described and controlled by an FCB. The bandwidth associated with the storing and distribution of data is optimized by chaining the data packets in different types of queues, or operating without chaining outside a queue. When a frame is in an output queue, the third word contains an RFCBA for egress of the frame to a line port, and an MCID for ingress from an output queue to a switch port. The RFCBA and the MCID have multicast capabilities. The format does not require a third word when a frame is in an input queue.

Abstract translation: 用于将信息处理系统链接在一起的通信网络利用交换网络在发送者和接收者之间传送数据。 每个单独的数据包由FCB描述和控制。 与存储和分发数据相关联的带宽通过将数据分组链接在不同类型的队列中进行优化，或者在不在队列外链接的情况下运行。 当帧位于输出队列中时，第三个字包含用于将帧从线路端口排出的RFCBA，以及用于从输出队列进入交换机端口的MCID。 RFCBA和MCID具有多播功能。 当帧在输入队列中时，格式不需要第三个字。

公开(公告)号：US20080089358A1

公开(公告)日：2008-04-17

申请号：US11953820

申请日：2007-12-10

Applicant: Claude BASSO ,  Jean CALVIGNAC ,  Chih-jen CHANG ,  Philippe DAMON ,  Natarajan VAIDHYANATHAN ,  Fabrice VERPLANKEN ,  Colin VERRILLI

Inventor： Claude BASSO ,  Jean CALVIGNAC ,  Chih-jen CHANG ,  Philippe DAMON ,  Natarajan VAIDHYANATHAN ,  Fabrice VERPLANKEN ,  Colin VERRILLI

IPC: H04J3/22 ,  H04J3/16

CPC classification number: H04L12/40032 ,  H04L12/413 ,  H04L49/90 ,  H04L69/12 ,  H04L69/16 ,  H04L69/161 ,  H04L69/18 ,  H04L69/323 ,  H04L69/324

Abstract: A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.

Abstract translation: 根据本发明的系统和方法允许在可以使用相同引脚容纳10G和1G的源的服务器环境中使用适配器。 这是通过使用可以容纳两个数据源的高速串行器/解串器（高速serdes）来实现的。 高速serdes允许在NIC上使用相对较低的参考时钟速度来提供数据源的适当时钟，并且还允许设置不同的模式以适应不同的数据源。 最后，该系统允许适配器为多个数据源使用相同的引脚。

公开(公告)号：US07277982B2

公开(公告)日：2007-10-02

申请号：US10899937

申请日：2004-07-27

Applicant: Jean L. Calvignac ,  Chih-jen Chang ,  Gordon T. Davis ,  Fabrice J. Verplanken

Inventor： Jean L. Calvignac ,  Chih-jen Chang ,  Gordon T. Davis ,  Fabrice J. Verplanken

IPC: G06F12/00

CPC classification number: G06F13/1642

Abstract: Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.

Abstract translation: 访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。 这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。 仲裁器首先将DRAM访问划分为写访问和读访问。 访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。 基于写入队列状态，写入接收数据包在存储体之间旋转。 每个存储体的写入队列的状态也可以用于系统流控制。 仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。