Method for equalizing input signal to generate equalizer output signal and associated parametric equalizer

    公开(公告)号:US11601753B2

    公开(公告)日:2023-03-07

    申请号:US17344907

    申请日:2021-06-10

    Abstract: A parametric equalizer includes an equalizer circuit, a first protection circuit, a second protection circuit, and a first addition circuit. The equalizer circuit is arranged to receive an input signal, and process the input signal to generate an output signal. The first protection circuit is arranged to generate a first protection signal according to the output signal, the input signal, and a first processed signal. The second protection circuit is arranged to generate a second protection signal according to the input signal and a second processed signal. The first addition circuit is coupled to the first protection circuit and the second protection circuit, and is arranged to combine the first protection signal and the second protection signal to generate an equalizer output signal.

    Circuit and method for switching between ternary modulation and quaternary modulation

    公开(公告)号:US11489499B1

    公开(公告)日:2022-11-01

    申请号:US17396853

    申请日:2021-08-09

    Abstract: A switch circuit provides a first output signal and a second output signal for switching between ternary modulation and quaternary modulation for a target device. A first output signal is provided from one of a first signal, a second signal and a ground signal according to an input signal and a duty signal, wherein the first signal is generated through performing a one-bit left-shift operation for the input signal, and the second signal is generated through adding the input signal and the duty signal. A second output signal is provided from one of a third signal, a fourth signal and the ground signal according to the input signal and the duty signal, wherein the third signal is generated through subtracting the input signal from the duty signal, and the fourth signal is generated through performing a two's-complement transformation and the one-bit left-shift operation for the input signal.

    POST OVER-ERASE CORRECTION METHOD WITH AUTO-ADJUSTING VERIFICATION AND LEAKAGE DEGREE DETECTION

    公开(公告)号:US20220223213A1

    公开(公告)日:2022-07-14

    申请号:US17149689

    申请日:2021-01-14

    Abstract: A post over-erase correction (POEC) method with an auto-adjusting verification mechanism and a leakage degree detection function detects gm degradation or leakage degree of flash cells before or after entering the POEC process. When a preset condition is satisfied, the auto-adjusting verification mechanism of the POEC is switched on to further reduce leakage current. After cycling, the POEC repairs Vt of over-erased cells to a higher level to solve leakage issues. The erase shot count increases due to slower erase speeds after cycling. Therefore, the cycling degree of flash cells is detected by observing the shot number that the erase operation used. When the leakage phenomenon becomes serious, the bit line (BL) leakage current, amount of repaired BLs, and over-erase correction (OEC) shot number will increase during the OEC procedure. Therefore, the leakage degree of flash cells can be detected by inspecting the above data.

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