公开(公告)号：US20150177759A1

公开(公告)日：2015-06-25

申请号：US14580851

申请日：2014-12-23

Applicant: ESS Technology, Inc.

Inventor： A. Martin Mallinson

IPC: G05F1/575

CPC classification number: G05F1/575 ,  G05F1/618

Abstract: A voltage regulator for providing a constant voltage to a circuit is described in which a series regulator acts as the current source for a shunt regulator and the series regulator in turn is controlled by the current diverted from the output by the shunt regulator. The current being diverted by the shunt regulator is measured, either directly or by measuring a related operating parameter. When current below or above a certain desired amount is being diverted from the load by the shunt regulator, a signal is sent to the series regulator causing the series regulator to provide more or less current respectively, so that the shunt regulator again diverts the desired amount of current and the output voltage remains constant. This configuration results in efficiency near that of a series regulator while maintaining the better frequency response of a shunt regulator.

Abstract translation: 描述了用于向电路提供恒定电压的电压调节器，其中串联调节器用作分流调节器的电流源，并且串联调节器又由分流调节器从输出转移的电流控制。 由分流调节器转移的电流可以直接测量或通过测量相关的操作参数进行测量。 当低于或高于一定期望量的电流由分流调节器从负载转移时，信号被发送到串联调节器，使得串联调节器分别提供更多或更少的电流，使得并联调节器再次转移所需量 的电流和输出电压保持不变。 该配置导致效率接近串联调节器的效率，同时保持分流调节器的更好的频率响应。

公开(公告)号：US08994422B2

公开(公告)日：2015-03-31

申请号：US14055772

申请日：2013-10-16

Applicant: ESS Technology, Inc.

Inventor： Hu Jing Yao ,  Dustin Dale Forman ,  A. Martin Mallinson

IPC: H03L7/06 ,  H03L7/195 ,  H03L7/18 ,  H03L7/23

CPC classification number: H03L7/195 ,  H03L7/18 ,  H03L7/235

Abstract: A method and system is disclosed in which the phase detector in a phase-locked loop is able to run at the fastest speed appropriate for a reference signal. A frequency offset is added to the output frequency of the phase-locked loop, to alter the frequency fed to the frequency divider which would receive the output frequency in a conventional PLL to an intermediate frequency. The frequency offset is selected so that the ratio of the intermediate frequency to the reference frequency is a simple fraction, and preferably an integer, i.e., the intermediate frequency is a multiple of the reference frequency. In cases where the relationship between the output frequency and the reference frequency is largely relatively prime, the phase detector is thus able to receive signals at the frequency of the reference signal and operate at the fastest speed appropriate for the reference signal.

Abstract translation: 公开了一种方法和系统，其中锁相环中的相位检测器能够以适合于参考信号的最快速度运行。 频率偏移被添加到锁相环的输出频率，以改变馈送到分频器的频率，该分频器将常规PLL中的输出频率接收到中频。 选择频率偏移，使得中频与参考频率的比率是简单的分数，优选地是整数，即中频是参考频率的倍数。 在输出频率和参考频率之间的关系很大程度上相对于素数的情况下，相位检测器因此能够以参考信号的频率接收信号并且以适合于参考信号的最快速度进行操作。

公开(公告)号：US20150003575A1

公开(公告)日：2015-01-01

申请号：US14321390

申请日：2014-07-01

Applicant: ESS Technology, Inc.

Inventor： A. Martin Mallinson

IPC: H04L7/00

CPC classification number: H03H17/06 ,  H03H17/0229 ,  H03H17/0248 ,  H03H17/0286 ,  H03H17/0294 ,  H03H21/0012 ,  H03H21/002

Abstract: FIR filters for compensating for fixed pattern jitter, and methods of constructing the same, are disclosed. In one embodiment, a FIR filter filters a signal having a desired frequency component, with the coefficients of the FIR filter selected so that the filter is the equivalent of two combined FIR filters, one having the desired frequency at the filter's peak output frequency, and a second in which the signal is delayed by a time equal to half of a period of a different frequency which is desired to be removed from the on signal. In another embodiment, a FIR filter includes a delay line with a total delay longer than the period of the jitter. A signal is passed down the delay line, the number of signal edges that have occurred as the signal passes each delay element in the counted. Drivers corresponding to the delay elements in which a number of signal edges occur at the desired frequency during the period of fixed pattern jitter activate impedance elements attached to those delay elements. A processor configures the activated impedance elements to provide the desired filter response.

Abstract translation: 公开了用于补偿固定模式抖动的FIR滤波器及其构造方法。 在一个实施例中，FIR滤波器对具有期望频率分量的信号进行滤波，其中选择FIR滤波器的系数，使得滤波器等效于两个组合的FIR滤波器，一个具有滤波器峰值输出频率处的期望频率， 其中信号被延迟等于期望从接通信号去除的不同频率的周期的一半的时间的第二。 在另一个实施例中，FIR滤波器包括具有比抖动周期长的总延迟的延迟线。 信号沿着延迟线传递，当信号通过计数的每个延迟元件时，发生的信号边沿的数量。 对应于在固定模式抖动的周期期间以期望频率出现的信号边缘数量的延迟元件的驱动器激活连接到这些延迟元件的阻抗元件。 处理器配置激活的阻抗元件以提供期望的滤波器响应。

公开(公告)号：US08773197B2

公开(公告)日：2014-07-08

申请号：US13683637

申请日：2012-11-21

Applicant: ESS Technology, Inc.

Inventor： Dustin Dale Forman ,  Trevor Blake Lynch-Staunton ,  Montana T. C. Reid

IPC: H03F3/38

CPC classification number: H03F3/217 ,  H03F1/3205 ,  H03F3/2171 ,  H03F3/2175

Abstract: The present application describes an apparatus and method for reducing distortion in a class-D amplifier. The power output section of the amplifier is driven by an adjusted PWM signal, rather than by a PWM signal created directly from the input analog signal. A reference output, designed to closely track the input analog signal, is compared to the amplifier output. The resulting difference is an error signal which is inverted and summed with a second analog signal corresponding to the directly created PWM signal and changes the timing of the voltage transitions of the second analog signal. The changed voltage transitions are used to create the adjusted PWM signal. The inversion of the error signal causes negative feedback which results in the adjustment of the PWM signal being in a direction which reduces the error signal and thus the distortion of the amplifier.

Abstract translation: 本申请描述了用于减少D类放大器中的失真的装置和方法。 放大器的功率输出部分由调整后的PWM信号驱动，而不是直接由输入模拟信号产生的PWM信号驱动。 与输出模拟信号紧密跟踪的参考输出与放大器输出进行比较。 所产生的差异是将与直接产生的PWM信号对应的第二模拟信号反相并相加并且改变第二模拟信号的电压转换的定时的误差信号。 改变的电压转换用于创建调整后的PWM信号。 误差信号的反转引起负反馈，导致PWM信号的调整在减小误差信号的方向上，从而导致放大器的失真。

公开(公告)号：US20140105269A1

公开(公告)日：2014-04-17

申请号：US14055785

申请日：2013-10-16

Applicant: ESS Technology, Inc.

Inventor： A. Martin Mallinson

IPC: H04L25/49

CPC classification number: H04L25/4902 ,  H03H17/0213 ,  H03H17/06

Abstract: A system and method for filtering an analog signal with a finite impulse response (FIR) filter that does not require analog delay elements are disclosed. An analog signal is pulse-width encoded, and the pulse-width encoded signal passed to a delay line comprising unclocked delay elements, such as logic gates, rather than clocked delay elements such as are used in conventional FIR filters. The propagation of the input signal is thus due only to the delay inherent in each gate, and occurs based upon when a signal reaches the gate rather than being caused by a clock signal. As with a conventional FIR filter, weighting elements having impedance are used to weigh the output of each delay element, and the resulting outputs summed to obtain a filtered output signal. For certain signals, such a circuit and method provides a simpler way of filtering than conventional filters.

Abstract translation: 公开了一种使用不需要模拟延迟元件的有限脉冲响应（FIR）滤波器对模拟信号进行滤波的系统和方法。 模拟信号被脉冲宽度编码，并且脉冲宽度编码信号传递到包括诸如逻辑门之类的非锁定延迟元件的延迟线，而不是例如在常规FIR滤波器中使用的定时延迟元件。 因此，输入信号的传播仅由于每个栅极固有的延迟而发生，并且基于何时信号到达门而不是由时钟信号引起。 与常规FIR滤波器一样，具有阻抗的加权元件用于称量每个延迟元件的输出，并且所得到的输出相加以获得经滤波的输出信号。 对于某些信号，这种电路和方法提供比常规滤波器更简单的滤波方式。

公开(公告)号：US20140073279A1

公开(公告)日：2014-03-13

申请号：US14022155

申请日：2013-09-09

Applicant: ESS Technology, Inc.

Inventor： Robert Lynn Blair ,  A. Martin Mallinson

IPC: H04B1/26

CPC classification number: H04B1/26 ,  H04B1/0007

Abstract: A method and system is disclosed for simultaneously down-converting multiple selected signals, such as RF signals, into adjacent ranges in an intermediate frequency band so that the total resulting bandwidth, and thus the sampling rate required to digitize the signal, is minimized. A first signal is down-converted into a range starting at a lowest selected frequency in the IF band. The next signal is down-converted, into a range higher than, but near or adjacent to, the down-converted range of the first signal, and so on. A guard band may be left between the signals if desired. In this way, the selected signals occupy the minimum bandwidth required. When the selection of signals to be down-converted is changed, the frequency ranges are dynamically adjusted so that the signals being down-converted always occupy the lowest ranges of the IF band.

Abstract translation: 公开了一种方法和系统，用于同时将多个所选信号（例如RF信号）下变频到中间频带中的相邻范围，使得总结果带宽以及因此将信号数字化所需的采样率最小化。 第一信号被下变频到从IF频段中最低选定频率开始的范围。 下一个信号被降频转换成高于第一信号的下变频范围但接近或相邻的范围，等等。 如果需要，保护带可能会留在信号之间。 以这种方式，所选择的信号占用所需的最小带宽。 当要降低转换的信号的选择被改变时，动态地调节频率范围，使得被降频转换的信号总是占据IF频带的最低范围。

公开(公告)号：US20130254253A1

公开(公告)日：2013-09-26

申请号：US13848272

申请日：2013-03-21

Applicant: ESS TECHNOLOGY, INC.

Inventor： A. Martin Mallinson

IPC: G06G7/02

CPC classification number: G06G7/02 ,  G06G7/625 ,  H03H15/023

Abstract: A circuit that provides a rotating coefficient FIR filter with all necessary coefficient sets present at the same time, without the need for delay elements, devices providing for adjustable impedances, or buffers is described. An input signal is sampled in a round robin fashion by a plurality of switches and capacitors. The capacitors are connected directly to sets of impedance devices. Each set of impedance devices implements the coefficients of the desired frequency response of the filter, adjusted to compensate for the decay of samples in the capacitors between samples. The impedance devices in each set are connected to the capacitors in a different order from each other set, so that each set of impedance devices will produce the desired frequency response when a different one of the capacitor contains a new sample of the input signal. Switches connect the sets of impedance devices to an output and a virtual ground, only one switch being connected to the output at a time to provide the output signal.

Abstract translation: 描述了提供具有同时存在的所有必要系数组的旋转系数FIR滤波器的电路，而不需要延迟元件，提供可调节阻抗的装置或缓冲器。 通过多个开关和电容器以循环方式对输入信号进行采样。 电容器直接连接到一组阻抗器件上。 每组阻抗器件实现滤波器所需频率响应的系数，被调整以补偿样本之间的电容器中样本的衰减。 每组中的阻抗器件以彼此不同的顺序连接到电容器，使得当电容器中的不同电容器包含输入信号的新采样时，每组阻抗器件将产生所需的频率响应。 开关将阻抗器件组连接到输出和虚拟接地，一次只有一个开关连接到输出端以提供输出信号。

公开(公告)号：US20040233088A1

公开(公告)日：2004-11-25

申请号：US10444813

申请日：2003-05-22

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: H03M001/66 ,  H03M003/00

CPC classification number: H03M3/504

Abstract: A circuit is provided having a secondary semi-analog FIR filter connected to a primary filter via a coefficient to reduce the size of the sizes of the resistors used in the primary filter. The coefficient may be one or more intermediate resistors connected between separate resistor/voltage driver banks that make up the FIR filter. The result is a circuit that takes up less chip space required to accommodate the required resistance for a digital to analog converter (DAC). The invention configures the resistor structure to produce the same output result as a conventional circuit, but with smaller resistor values that take up less surface area on the chip.

Abstract translation: 提供具有通过系数连接到初级滤波器的次级半模拟FIR滤波器以减小在初级滤波器中使用的电阻器的尺寸的尺寸的电路。 该系数可以是连接在构成FIR滤波器的分立电阻/电压驱动器组之间的一个或多个中间电阻器。 结果是一个电路占用更少的芯片空间，以适应数模转换器（DAC）所需的电阻。 本发明构造了电阻器结构以产生与常规电路相同的输出结果，但是具有较小的电阻值，其占用较小的芯片表面积。

公开(公告)号：US20040213364A1

公开(公告)日：2004-10-28

申请号：US10810313

申请日：2004-03-26

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: H04L027/06

CPC classification number: H03H17/027 ,  H03H2218/06 ,  H04L27/2601

Abstract: A signal processor has a plurality of channels, each channel configured to receive an input signal stream, to reduce the signal to a direct current signal and to process the signal according to the stream signal. Each channel also has a plurality of low pass filters configured to filter in-phase and quadrature-phase modulator outputs with a first low pass filter and to filter a reference quadrature signals, and a gain control configured to re-modulate gain adjusted output signals with the filtered quadrature signals. The processor further includes an inverter to invert the in-phase filtered reference signal and means to multiply the quadrature gain adjusted output signal.

Abstract translation: 信号处理器具有多个通道，每个通道被配置为接收输入信号流，以将信号减小到直流信号，并根据流信号处理信号。 每个通道还具有多个低通滤波器，其被配置为用第一低通滤波器对同相和正交相位调制器输出进行滤波，并对基准正交信号进行滤波;以及增益控制，被配置为重新调制增益调整的输出信号， 滤波后的正交信号。 处理器还包括反相器，用于反相同相滤波的参考信号，以及将正交增益调整的输出信号相乘的装置。

公开(公告)号：US20040212526A1

公开(公告)日：2004-10-28

申请号：US10810310

申请日：2004-03-26

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: H03M001/66 ,  H03M001/00

CPC classification number: H03M1/0604 ,  H03M1/682 ,  H03M1/765

Abstract: An improved segmented analog to digital converter is provided, configured with a novel method of compensating current flow in secondary or successive segmented elements. In operation, dual current devices initially load, then subsequently unload a cascade of resistor networks connected to the secondary or successive voltage segmenting elements, preventing the perturbation of precise operation of the primary or preceding elements. In contrast to conventional approaches, the improved converter obviates the need for a buffer or amplifier to isolate the secondary and successive voltage segmenting elements from the primary or preceding elements.

Abstract translation: 提供了一种改进的分段模数转换器，其配置有补偿次级或连续分段元件中的电流的新颖方法。 在操作中，双电流装置最初加载，随后卸载连接到次级或连续电压分段元件的级联的电阻网络，以防止主要或先前元件的精确操作的扰动。 与常规方法相比，改进的转换器不需要缓冲器或放大器来隔离次级和连续的电压分段元件与初级元件或先前元件。