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公开(公告)号：US11653441B2
公开(公告)日：2023-05-16
申请号：US16951695
申请日：2020-11-18
Inventor： Julien Didion , Thierry Lapergue
CPC classification number: H05K1/025 , H04B1/16 , H05K1/181 , H05K2201/09272 , H05K2201/09281 , H05K2201/10045 , H05K2201/10098
Abstract: A device includes a printed circuit board substrate, an antenna connected to the printed circuit board substrate, an amplifier connected to the printed circuit board substrate, and a matching track having a first end electrically connected to an input of the amplifier and a second end electrically connected to an output of the antenna. The matching track has an outgrowth that is symmetrical along a median axis of the outgrowth. The matching track is rectilinear and has a constant width over an initial part extending between the widening area and the first end. A median axis of the initial part and the median axis of the outgrowth form an angle comprised between 60 and 120°.
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公开(公告)号：US20230113667A1
公开(公告)日：2023-04-13
申请号：US18065475
申请日：2022-12-13
Inventor： Jawad Benhammadi , Sylvain Meyer
IPC: G06F13/24 , G06F13/16 , G06F21/85 , H03K19/20 , G06F1/3237
Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal likely to emanate from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.
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公开(公告)号：US20230098647A1
公开(公告)日：2023-03-30
申请号：US18062980
申请日：2022-12-07
Applicant: STMicroelectronics (Alps) SAS
Inventor： Michel Bouche
Abstract: An embodiment of the present disclosure relates to an electronic circuit including a first switch coupling a first node of the circuit to an input/output terminal of the circuit; a second switch coupling the first node to a second node of application of a fixed potential; and a highpass filter having an input coupled to the terminal and an output coupled to a control terminal of the second switch.
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公开(公告)号：US20230087239A1
公开(公告)日：2023-03-23
申请号：US18059812
申请日：2022-11-29
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS , STMicroelectronics S.r.l.
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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公开(公告)号：US20220399880A1
公开(公告)日：2022-12-15
申请号：US17830864
申请日：2022-06-02
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Inventor： Antonino Conte , Marco Ruta , Michelangelo Pisasale , Thomas Jouanneau
Abstract: In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.
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Patent Agency Ranking
公开(公告)号：US11496170B2
公开(公告)日：2022-11-08
申请号：US17180751
申请日：2021-02-20
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Abstract: The present disclosure relates to a method for controlling a device comprising an oscillation circuit, configured to provide a clock signal to a radio frequency circuit, and an antenna, in which the enabling of the passage of the signal from the circuit to the antenna is delayed with respect to an instant from which a power amplifier of the circuit is enabled.
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77.发明申请公开(公告)号：US20220295007A1
公开(公告)日：2022-09-15
申请号：US17649858
申请日：2022-02-03
Inventor： Nicolas Moeneclaey , Samuel Foulon
IPC: H04N5/3745 , G01J1/42 , G01J1/44
Abstract: A photosensitive device includes a peripheral circuit semiconductor region, a photosensitive circuit semiconductor region including at least one group of at least two photosensitive elements configured to generate a photoelectric signal on a node called critical node. The device further includes an integrator circuit per group of photosensitive elements, each including: a differential circuit for each photosensitive element of the group, in the photosensitive circuit semiconductor region, an amplification circuit, in the peripheral circuit semiconductor region, and a feedback circuit for each photosensitive element of the group, comprising a capacitive element located in the photosensitive circuit semiconductor region coupled between the output node of the amplification circuit and the respective critical node.
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公开(公告)号：US20220179822A1
公开(公告)日：2022-06-09
申请号：US17457553
申请日：2021-12-03
Applicant: STMICROELECTRONICS SA , STMicroelectronics (Alps) SAS
Inventor： Michael Soulie , Thomas Martin
Abstract: According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.
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公开(公告)号：US11342908B2
公开(公告)日：2022-05-24
申请号：US17145863
申请日：2021-01-11
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Abstract: An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.
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公开(公告)号：US20220151056A1
公开(公告)日：2022-05-12
申请号：US16951695
申请日：2020-11-18
Inventor： Julien Didion , Thierry Lapergue
Abstract: A device includes a printed circuit board substrate, an antenna connected to the printed circuit board substrate, an amplifier connected to the printed circuit board substrate, and a matching track having a first end electrically connected to an input of the amplifier and a second end electrically connected to an output of the antenna. The matching track has an outgrowth that is symmetrical along a median axis of the outgrowth. The matching track is rectilinear and has a constant width over an initial part extending between the widening area and the first end. A median axis of the initial part and the median axis of the outgrowth form an angle comprised between 60 and 120°.
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