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96 条记录 (耗时 0.021 秒)

    Ceramic capacitor
    6.
    发明授权
    Ceramic capacitor 有权
    陶瓷电容器

    公开(公告)号：US07889509B2

    公开(公告)日：2011-02-15

    申请号：US11513039

    申请日：2006-08-31

    申请人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

    发明人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

    IPC分类号： H05K7/00

    CPC分类号： H05K1/185 ,  H01G2/06 ,  H01G4/385 ,  H01L23/49816 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K3/4602 ,  H05K2201/10045 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

    摘要： A circuit board (10, 10″, 10′″) comprising: a board core (11) having a main core surface (12) and a rear core surface (13); a ceramic capacitor (101, 101′, 101″, 101′″, 101″″, 101″″′, 101″″″) having a main capacitor surface (102) and a rear capacitor surface (103), having a structure in which a first inner electrode layer (141) and a second inner electrode layer (142) are alternately stacked with a ceramic dielectric layer (105) interposed therebetween, and having a plurality of capacitor function units (107, 108) being electrically independent from each other, the ceramic capacitor (101, 101′, 101″, 101′″, 101″″, 101″″′, 101″″″) being buried in the board core (11) in a state where the main core surface (12) and the main capacitor surface (102) are directed in a same direction; and a buildup layer (31) having a structure in which an interlayer insulating layer (33, 35) and a conductor layer (42) are alternately stacked on the main core surface (12) and the main capacitor surface (102) and having a semiconductor integrated circuit device mounting region (23, 51, 52) for mounting a semiconductor integrated circuit device (21, 53, 54) having a plurality of processor cores (24, 25) on a surface (39) of the buildup layer (31), wherein the plurality of capacitor function units (107, 108) are capable of being electrically connected to the plurality of processor cores (24, 25), respectively.

    摘要翻译： 一种电路板（10,10“，10”），包括：具有主芯表面（12）和后芯表面（13）的板芯（11）; 具有主电容器表面（102）和后电容器表面（103）的陶瓷电容器（101,101'，101“，101”，101“”，101“”，101“”“）， 其中第一内部电极层（141）和第二内部电极层（142）交替层叠有介于其间的陶瓷介电层（105），并且具有多个电容器功能单元（107,108），其电独立于 相互之间的陶瓷电容器（101,101'，101“，101”，101“，101”，101“”101“”）被埋在板芯11中， （12）和主电容器表面（102）指向相同的方向; 以及具有层间绝缘层（33,35）和导体层（42）在主芯面（12）和主电容器表面（102）上交替层叠的结构的积层（31），具有 半导体集成电路器件安装区域（23,51,52），用于安装具有多个处理器核心（24,25）的半导体集成电路器件（21,53,54），所述多个处理器核心（24,25）在所述生成层（31）的表面（39）上 ），其中所述多个电容器功能单元（107,108）能够分别电连接到所述多个处理器核（24,25）。

    Embedded type multifunctional integrated structure and method for manufacturing the same
    7.
    发明申请
    Embedded type multifunctional integrated structure and method for manufacturing the same 失效
    嵌入式多功能一体化结构及其制造方法

    公开(公告)号：US20090130369A1

    公开(公告)日：2009-05-21

    申请号：US11984559

    申请日：2007-11-20

    申请人： Chien-Hao Huang ,  Wen-Chih Li

    发明人： Chien-Hao Huang ,  Wen-Chih Li

    IPC分类号： B32B5/00 ,  B05D5/12

    CPC分类号： H05K1/0234 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/141 ,  H05K1/167 ,  H05K1/185 ,  H05K3/3442 ,  H05K3/4611 ,  H05K3/4688 ,  H05K2201/09181 ,  H05K2201/09309 ,  H05K2201/10045 ,  Y10T428/239

    摘要： An embedded type multifunctional integrated structure and a method for manufacturing the same are disclosed. The present invention utilizes the concept of multi-layer design to integrated more than two passive components on a component structure that would be adhered to a substrate. Hence, the embedded type multifunctional integrated structure has an OCP function, an OVP function, an anti-EMI function, and an anti-ESD function at the same time. Therefore, the present invention effectively integrated two or more than one passive components in order to increase function of the embedded type multifunctional integrated structure. Moreover, the present invention effectively reduces the size of the passive components on a PCB and reduces the number of solder joints.

    摘要翻译： 公开了一种嵌入式多功能一体化结构及其制造方法。 本发明利用多层设计的概念将多于两个的无源部件集成在将粘附到基板上的部件结构上。 因此，嵌入式多功能一体化结构同时具有OCP功能，OVP功能，抗EMI功能和抗ESD功能。 因此，为了增加嵌入式多功能一体化结构的功能，本发明有效地集成了两个或多个无源部件。 此外，本发明有效地减小了PCB上的无源部件的尺寸，并且减少了焊点的数量。

    Amplifier with feedback bridge
    8.
    发明授权
    Amplifier with feedback bridge 有权
    带反馈桥的放大器

    公开(公告)号：US07417498B2

    公开(公告)日：2008-08-26

    申请号：US11452405

    申请日：2006-06-14

    申请人： Dirk Wiegner ,  Thomas Merk

    发明人： Dirk Wiegner ,  Thomas Merk

    IPC分类号： H03F1/34

    CPC分类号： H03F3/195 ,  H03F2200/144 ,  H03F2200/147 ,  H03F2200/451 ,  H05K1/0243 ,  H05K1/181 ,  H05K2201/10045 ,  H05K2201/10166 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y02P70/611

    摘要： An amplifier, in particular for RF-applications, comprises a circuit board (2), at least one amplifier stage with at least one transistor package (8) arranged on the circuit board (2), and a feedback path (12) around the at least one transistor package (8), said feedback path (12) comprising a feedback element (15) with at least one capactive (C) element for blocking the flow of direct current through the feedback path (12) and preferably further comprising at least one inductive (L) and/or resistive element (R). In order to reduce negative effects on the performance of the amplifier due to long printed feedback lines, the feedback path (12) in an amplifier according to the invention is formed of a feedback bridge (9) comprising two feedback lines (13, 14) extending out of the plane of the circuit board (2) from two contact flags (10, 11) of the transistor package (8), and the feedback element (15) bridging over the transistor package (8) between the two feedback lines (13, 14).

    摘要翻译： 特别是用于RF应用的放大器包括电路板（2），至少一个具有布置在电路板（2）上的至少一个晶体管封装（8）的放大器级，以及围绕 至少一个晶体管封装（8），所述反馈路径（12）包括具有至少一个负载（C）元件的反馈元件（15），用于阻断通过所述反馈路径（12）的直流电流，并且优选地还包括 至少一个电感（L）和/或电阻元件（R）。 为了减少由于长的印刷反馈线引起的放大器的性能的负面影响，根据本发明的放大器中的反馈路径（12）由包括两个反馈线（13,14）的反馈桥（9）形成， 从晶体管封装（8）的两个接触标记（10,11）延伸出电路板（2）的平面，并且反馈元件（15）跨接在两个反馈线之间的晶体管封装（8）上 13,14）。

    Surface mounting chip network component
    10.
    发明申请
    Surface mounting chip network component 有权
    表面安装芯片网络组件

    公开(公告)号：US20050253681A1

    公开(公告)日：2005-11-17

    申请号：US10506947

    申请日：2002-03-25

    申请人： Eiji Kobayashi

    发明人： Eiji Kobayashi

    IPC分类号： H01C1/01 ,  H01G2/06 ,  H05K3/34

    CPC分类号： H01G2/065 ,  H01C1/01 ,  H05K3/3442 ,  H05K2201/09181 ,  H05K2201/09781 ,  H05K2201/10045 ,  Y02P70/613

    摘要： A surface mounting chip network component in which a network having three or more odd number of terminals are formed on the surface of an insulating substrate and Tomb Stone Phenomenon is suppressed. Even number of network circuits are formed on the surface of the insulating substrate (2) and the same number of terminals (1) are arranged, respectively, on the opposite sides of the insulating substrate (2). Alternatively, even number of network circuits are formed on the surface of the insulating substrate (2) and the terminals (1) are arranged on the side edges of the insulating substrate (2) point-symmetrically with respect to the center of the surface of the insulating substrate (2).

    摘要翻译： 在绝缘基板的表面上形成具有三个以上奇数个端子的网络的表面安装芯片网络部件被抑制。 在绝缘基板（2）的表面上形成有多个网络电路，并且在绝缘基板（2）的相对侧分别配置有相同数量的端子（1）。 或者，在绝缘基板（2）的表面上形成有多个网络电路，并且端子（1）相对于表面的中心点对称地配置在绝缘基板（2）的侧缘 绝缘基板（2）。