公开(公告)号：US07451121B2

公开(公告)日：2008-11-11

申请号：US11237562

申请日：2005-09-27

Applicant: Youfeng Wu ,  Mauricio Breternitz, Jr.

Inventor： Youfeng Wu ,  Mauricio Breternitz, Jr.

IPC: G06F15/18 ,  G06N3/00 ,  G06N3/12

CPC classification number: G06N3/126 ,  G06F9/3017

Abstract: A method to compress microcode utilizing a genetic algorithm includes generating a population of chromosomes, each chromosome including one or more elements that indicate a cluster to which a portion of microcode memory belongs. The method further includes determining a fitness value of each chromosome and modifying the population of chromosomes based on the fitness values of the chromosomes to generate a new population of chromosomes. In addition, the method includes compressing the microcode memory using a cluster-based compression technique, wherein clusters are selected according to a chromosome from the new population with the best fitness value. Other embodiments are also disclosed.

Abstract translation: 使用遗传算法压缩微码的方法包括生成染色体群体，每个染色体包括指示微代码存储器的一部分所属的簇的一个或多个元件。 该方法还包括根据染色体的适应度值确定每个染色体的适应度值和修饰染色体群体以产生新的染色体群体。 此外，该方法包括使用基于簇的压缩技术来压缩微代码存储器，其中根据来自具有最佳适应度值的新群体的染色体来选择簇。 还公开了其他实施例。

公开(公告)号：US07448031B2

公开(公告)日：2008-11-04

申请号：US10739500

申请日：2003-12-17

Applicant: Youfeng Wu

Inventor： Youfeng Wu

IPC: G06F9/45

CPC classification number: G06F12/0888 ,  G06F8/4442 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F12/0897

Abstract: Methods and apparatus to compile a software program to manage parallel μ caches are disclosed. In an example method, a compiler attempts to schedule a software program such that load instructions in a first set of load instructions has a first predetermine latency greater than the latency of the first cache. The compiler also marks a second set of load instructions with a latency less than the first predetermined latency to access the first cache. The compiler attempts to schedule the software program such that the load instruction in a third set have at least a second predetermined latency greater than the latency of the second cache. The compiler identifies a fourth set of load instructions in the scheduled software program having less than the second predetermined latency and marks the fourth set of load instructions to access the second cache.

Abstract translation: 公开了编译软件程序来管理并行的多个高速缓存的方法和装置。 在示例性方法中，编译器尝试调度软件程序，使得第一组加载指令中的加载指令具有大于第一高速缓存的等待时间的第一预定延迟。 编译器还标记第二组加载指令，其延迟小于第一预定延迟以访问第一高速缓存。 编译器尝试调度软件程序，使得第三组中的加载指令具有比第二高速缓存的等待时间更长的至少第二预定等待时间。 编译器在预定软件程序中识别具有小于第二预定等待时间的第四组加载指令，并标记第四组加载指令以访问第二高速缓存。

公开(公告)号：US20080147714A1

公开(公告)日：2008-06-19

申请号：US11642314

申请日：2006-12-19

Applicant: Mauricio Breternitz ,  Youfeng Wu ,  Peter G. Sassone ,  Jeffrey P. Rupley ,  Wesley Attrot ,  Bryan Black

Inventor： Mauricio Breternitz ,  Youfeng Wu ,  Peter G. Sassone ,  Jeffrey P. Rupley ,  Wesley Attrot ,  Bryan Black

IPC: G06F17/30

CPC classification number: G06F12/0864 ,  Y10S707/99943

Abstract: Implementation of a Bloom filter using multiple single-ported memory slices. A control value is combined with a hashed address value such that the resultant address value has the property that one, and only one, of the k memories or slices is selected for a given input value, a, for each bank. Collisions are thereby avoided and the multiple hash accesses for a given input value, a, may be performed concurrently. Other embodiments are also described and claimed.

Abstract translation: 使用多个单端口存储器片的Bloom过滤器的实现。 控制值与散列地址值组合，使得所得到的地址值具有对于每个存储体的给定输入值a选择k个存储器或片中仅一个且仅一个的属性。 因此避免了冲突，并且可以同时执行给定输入值a的多个哈希访问。 还描述和要求保护其他实施例。

公开(公告)号：US20080126764A1

公开(公告)日：2008-05-29

申请号：US11528801

申请日：2006-09-27

Applicant: Youfeng Wu ,  Cheng Wang ,  Ho-seop Kim

Inventor： Youfeng Wu ,  Cheng Wang ,  Ho-seop Kim

IPC: G06F9/44 ,  G06F9/318

CPC classification number: G06F9/466

Abstract: Dynamic optimization of application code is performed by selecting a portion of the application code as a possible transaction. A transaction has a property that when it is executed, it is either atomically committed or atomically aborted. Determining whether to convert the selected portion of the application code to a transaction includes determining whether to apply at least one of a group of code optimizations to the portion of the application code. If it is determined to apply at least one of the code optimizations of the group of optimizations to the portion of application code, then the optimization is applied to the portion of the code and the portion of the code is converted to a transaction.

Abstract translation: 通过选择应用代码的一部分作为可能的事务来执行应用代码的动态优化。 事务有一个属性，当它被执行时，它被原子地提交或原子地中止。 确定是否将应用程序代码的所选部分转换为事务包括确定是否将应用程序代码的一部分中的至少一个代码优化组合应用。 如果确定将优化组的代码优化中的至少一个应用于应用代码的部分，则优化被应用于代码的该部分，并将该部分代码转换为事务。

公开(公告)号：US20080120590A1

公开(公告)日：2008-05-22

申请号：US11603375

申请日：2006-11-22

Applicant: Cheng Wang ,  Youfeng Wu ,  Wei-Yu Chen ,  Zhiwei Ying

Inventor： Cheng Wang ,  Youfeng Wu ,  Wei-Yu Chen ,  Zhiwei Ying

IPC: G06F9/44

CPC classification number: G06F9/466 ,  G06F8/41

Abstract: In general, in one aspect, the disclosure describes a method to detect a transaction and direct non transactional memory (TM) user functions within the transaction. The non TM user functions are treated as TM functions and added to the TM list.

Abstract translation: 通常，在一个方面，本公开描述了一种检测事务中的交易和直接非事务性存储器（TM）用户功能的方法。 非TM用户功能被视为TM功能并添加到TM列表中。

公开(公告)号：US20070022279A1

公开(公告)日：2007-01-25

申请号：US11186240

申请日：2005-07-20

Applicant: Youfeng Wu ,  Sangwook Kim ,  Mauricio Breternitz ,  Herbert Hum

Inventor： Youfeng Wu ,  Sangwook Kim ,  Mauricio Breternitz ,  Herbert Hum

IPC: G06F9/44

CPC classification number: G06F12/06 ,  G06F8/4436 ,  G06F9/30178 ,  G06F2212/401

Abstract: An arrangement is provided for compressing microcode ROM (“uROM”) in a processor and for efficiently accessing a compressed “uROM”. A clustering-based approach may be used to effectively compress a uROM. The approach groups similar columns of microcode into different clusters and identifies unique patterns within each cluster. Only unique patterns identified in each cluster are stored in a pattern storage. Indices, which help map an address of a microcode word (“uOP”) to be fetched from a uROM to unique patterns required for the uOP, may be stored in an index storage. Typically it takes a longer time to fetch a uOP from a compressed uROM than from an uncompressed uROM. The compressed uROM may be so designed that the process of fetching a uOP (or uOPs) from a compressed uROM may be fully-pipelined to reduce the access latency.

Abstract translation: 提供了一种用于在处理器中压缩微代码ROM（“uROM”）并有效访问压缩的“uROM”的装置。 可以使用基于聚类的方法来有效地压缩uROM。 该方法将相似的微代码列组合成不同的集群，并识别每个集群内的唯一模式。 每个集群中唯一标识的模式都存储在模式存储中。 帮助将从uROM获取的微代码字（“uOP”）的地址映射到uOP所需的唯一模式的索引可以存储在索引存储器中。 通常，从压缩的uROM获取uop比从未压缩的uROM获取更长的时间。 压缩的uROM可以被设计成使得从压缩的uROM获取uop（或uop）的过程可以被完全流水线化以减少访问等待时间。

公开(公告)号：US20060206886A1

公开(公告)日：2006-09-14

申请号：US11020340

申请日：2004-12-22

Applicant: Youfeng Wu ,  Mauricio Breternitz

Inventor： Youfeng Wu ,  Mauricio Breternitz

IPC: G06F9/45 ,  G06F9/44

CPC classification number: G06F8/4434

Abstract: In a method for reducing code size, replaceable subsets of instructions at first locations in areas of infrequently executed instructions in a set of instructions and target subsets of instructions at second locations in the set of instructions are identified, wherein each replaceable subset matches at least one target subset. If multiple target subsets of instructions match one replaceable subset of instructions, one of the multiple matching target subsets is chosen as the matching target subset for the one replaceable subset based on whether the multiple target subsets are located in regions of frequently executed code. For each of at least some of the replaceable subsets of instructions, the replaceable subset of instructions is replaced with an instruction to cause the matching target subset of instructions at the second location to be executed.

Abstract translation: 在减少代码大小的方法中，识别在一组指令中的不经常执行的指令的区域中的第一位置处的指令的可替换子集，以及指令集中的第二位置处的目标指令子集，其中每个可替换子集与至少一个 目标子集。 如果指令的多个目标子集匹配一个可替换的指令子集，则基于多个目标子集是否位于经常执行的代码的区域中，将多个匹配目标子集中的一个选择为一个可替换子集的匹配目标子集。 对于至少一些可替换的指令子集中的每一个，可替换的指令子集被替换为使得执行第二位置处的指令的匹配目标子集的指令。

公开(公告)号：US06848100B1

公开(公告)日：2005-01-25

申请号：US09541399

申请日：2000-03-31

Applicant: Youfeng Wu ,  Ali Adl-Tabatabai ,  David A. Berson ,  Jesse Fang ,  Rajiv Gupta

Inventor： Youfeng Wu ,  Ali Adl-Tabatabai ,  David A. Berson ,  Jesse Fang ,  Rajiv Gupta

IPC: G06F9/45 ,  G06F11/36

CPC classification number: G06F11/3612

Abstract: A hierarchical software profiling mechanism that gathers hierarchical path profile information has been described. Software to be profiled is instrumented with instructions that save an outer path sum when an inner region is entered, and restore the outer path sum when the inner region is exited. When the inner region is being executed, an inner path sum is generated and a profile indicator representing the inner path traversed is updated prior to the outer path sum being restored. The software to be profiled is instrumented using information from augmented control flow graphs that represent the software.

Abstract translation: 已经描述了收集分层路径简档信息的分层软件分析机制。 要进行分析的软件使用在输入内部区域时保存外部路径总和的指令进行测试，并且当内部区域退出时恢复外部路径和。 当正在执行内部区域时，生成内部路径和，并且在外部路径和恢复之前更新表示所遍历的内部路径的轮廓指示符。 要分析的软件使用来自表示软件的增强控制流程图的信息进行仪器化。

公开(公告)号：US06625725B1

公开(公告)日：2003-09-23

申请号：US09470113

申请日：1999-12-22

Applicant: Youfeng Wu ,  Jesse Fang

Inventor： Youfeng Wu ,  Jesse Fang

IPC: G06F944

CPC classification number: G06F9/3851 ,  G06F9/30076 ,  G06F9/3009 ,  G06F9/30123 ,  G06F9/3808 ,  G06F9/3828 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3857

Abstract: A speculative code reuse mechanism includes a reuse buffer, a main processing core and a reuse checking core. The reuse buffer includes inputs and outputs of previously executed instances of code reuse regions. Aliased reuse regions are regions that access memory locations that may change between executions of the region. When an aliased code reuse region is encountered and a matching instance exists in the reuse buffer, the main core speculatively executes code occurring after the reuse region, while the reuse checking core executes code from the reuse region to verify the matching instance. If the matching instance is verified, the speculative execution is committed, and if the matching instance is not verified, the speculative execution is squashed.

Abstract translation: 推测性代码重用机制包括重用缓冲区，主处理核心和重用检查核心。 重用缓冲器包括先前执行的代码重用区实例的输入和输出。 别名重用区域是访问可能在区域执行之间改变的存储器位置的区域。 当遇到一个别名的代码重用区域并且重用缓冲区中存在匹配的实例时，主内核推测地执行在重用区域之后发生的代码，而重用核心核心从重用区域执行代码来验证匹配的实例。 如果匹配实例被验证，则推测性执行被提交，并且如果匹配的实例未被验证，则推测性执行被压缩。

公开(公告)号：US20170185404A1

公开(公告)日：2017-06-29

申请号：US14998299

申请日：2015-12-26

Applicant: Vineeth Mekkat ,  Oleg Margulis ,  Jason M. Agron ,  Ethan Schuchman ,  Sebastian Winkel ,  Youfeng Wu ,  Gisle Dankel

Inventor： Vineeth Mekkat ,  Oleg Margulis ,  Jason M. Agron ,  Ethan Schuchman ,  Sebastian Winkel ,  Youfeng Wu ,  Gisle Dankel

IPC: G06F9/30

CPC classification number: G06F9/30185 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3865

Abstract: Embodiments of apparatus and methods for detecting and recovering from incorrect memory dependence speculation in an out-of-order processor are described herein. For example, one embodiment of a method comprises: executing a first load instruction; detecting when the first load instruction experiences a bad store-to-load forwarding event during execution; tracking the occurrences of bad store-to-load forwarding event experienced by the first load instruction during execution; controlling enablement of an S-bit in the first load instruction based on the tracked occurrences; generating a plurality of load operations responsive to an enabled S-bit in first load instruction, wherein execution of the plurality of load operations produces a result equivalent to that from the execution of the first load instruction.