公开(公告)号：US11158110B1

公开(公告)日：2021-10-26

申请号：US17142978

申请日：2021-01-06

Applicant: Arm Limited

Inventor： Edvard Fielding ,  Jorn Nystad

IPC: G06T15/04 ,  G06T7/44 ,  G06T15/00 ,  G06T15/80 ,  G06T11/00

Abstract: When sampling a pair of mipmaps when performing anisotropic filtering when sampling a texture to provide an output sampled texture value for use when rendering an output in a graphics processing system, more positions along an anisotropy direction are sampled in the more detailed mipmap level than in the less detailed mipmap level. Each position that is sampled may have a single sample taken for it, or may be supersampled.

公开(公告)号：US11023152B2

公开(公告)日：2021-06-01

申请号：US16510200

申请日：2019-07-12

Applicant: Arm Limited

Inventor： Jorn Nystad ,  Edvard Fielding ,  Jakob Axel Fries

IPC: G06F3/06 ,  G06T1/60

Abstract: When storing an array of data in memory, the data array is divided into a plurality of blocks, and for respective groups of the blocks that the data array has been divided into, a set of data representing the group of blocks that includes: for each block of the group of blocks, a set of data for that block of the group of blocks; and a size indication for each of one or more of the blocks of the group of blocks, the size indication for a block of a group of blocks indicating the size in memory of the set of data for that block of the group included in the stored set of data representing the group of blocks, is stored. A set of header data is also stored separately for each group of blocks of the data array.

公开(公告)号：US10331404B2

公开(公告)日：2019-06-25

申请号：US14584237

申请日：2014-12-29

Applicant: ARM Limited

Inventor： Jorn Nystad ,  Andreas Due Engh-Halstvedt ,  Simon Alex Charles

IPC: G06F7/483 ,  G06F9/30 ,  H03M7/24 ,  G06F5/00 ,  G06F7/499

Abstract: Apparatus for processing data includes processing circuitry 16, 18, 20, 22, 24, 26 and decoder circuitry 14 for decoding program instructions. The program instructions decoded include a floating point pre-conversion instruction which performs round-to-nearest ties to even rounding upon the mantissa field of an input floating number to generate an output floating point number with the same mantissa length but with the mantissa rounded to a position corresponding to a shorter mantissa field. The output mantissa field includes a suffix of zero values concatenated the rounded value. The decoder for circuitry 14 is also responsive to an integer pre-conversion instruction to quantise and input integer value using round-to-nearest ties to even rounding to form an output integer operand with a number of significant bits matched to the mantissa size of a floating point number to which the integer is later to be converted using an integer-to-floating point conversion instruction.

公开(公告)号：US20190096025A1

公开(公告)日：2019-03-28

申请号：US16139408

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Jorn Nystad ,  Carmelo Giliberto ,  Edvard Fielding

IPC: G06T1/20 ,  G06T1/60 ,  G06T11/00 ,  G06T15/00

Abstract: A texture mapping apparatus, e.g. of a graphics processing unit, comprises texture fetching circuitry operable to receive a set of weight values for a convolution operation and fetch from memory a set of input data values on which the convolution operation is to be performed. The texture mapping apparatus further comprises texture filtering circuitry operable to perform a convolution operation using the set of received weight values and the set of fetched input data values. The texture mapping apparatus can allow a graphics processing unit to perform a variety of convolution operations in an efficient manner.

公开(公告)号：US10152763B2

公开(公告)日：2018-12-11

申请号：US15218015

申请日：2016-07-23

Applicant: ARM Limited

Inventor： Jorn Nystad

IPC: G06T1/20

Abstract: The present disclosure relates to a graphics processors and graphics processing systems. In the graphics processor, the rasterizer may operate to identify pairs of fragments for a primitive being rendered for which not all the sampling positions in the fragments are covered by the primitive. When the fragments reach the fragment shader, corresponding execution threads may be spawned for execution by the fragment shader to process the fragments. A first part of the fragment shader program that uses the helper threads of the thread groups may then be executed. There may then be a merge instruction in the fragment shader program which operates to cause the active threads of the thread groups to be merged into a single, combined thread group. Following this thread group merger, the remaining program steps of the fragment shader program may be executed for the merged thread group.

公开(公告)号：US20170330372A1

公开(公告)日：2017-11-16

申请号：US15594969

申请日：2017-05-15

Applicant: ARM Limited

Inventor： Sandeep Kakarlapudi ,  Jorn Nystad ,  Andreas Due-Engh Halstvedt

IPC: G06T15/40 ,  G06T15/04 ,  G06T19/20 ,  G06T15/80 ,  G06T1/20 ,  G06T15/00

CPC classification number: G06T15/405 ,  G06T1/20 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/80 ,  G06T19/20 ,  H04N13/275

Abstract: A graphics processing pipeline comprises vertex shading circuitry that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline, to generate, inter alia, a separate vertex shaded position attribute value for each view of the plural different views. Tiling circuitry then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. Vertex shading circuitry then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further, to generate, inter alia, a single vertex shaded attribute value for the set of plural views.

公开(公告)号：US09805447B2

公开(公告)日：2017-10-31

申请号：US13690142

申请日：2012-11-30

Applicant: ARM Limited

Inventor： Andreas Engh-halstvedt ,  Jorn Nystad ,  Frode Heggelund ,  Ronny Pedersen

IPC: G06T5/00 ,  G06T15/50 ,  G06T11/40

CPC classification number: G06T5/002 ,  G06T11/40 ,  G06T15/503 ,  G06T2200/28

Abstract: When carrying out a second, higher level of anti-aliasing such as 8×MSAA, in a graphics processing pipeline 1 configured to “natively” support a first level of anti-aliasing, such as 4×MSAA, the rasterization stage 3, early Z (depth) and stencil test stage 4, late Z (depth) and stencil test stage 7, blending stage 9, and downsampling and writeback (multisample resolve) stage 11 of the graphics processing pipeline 1 process each graphics fragment or pixel that they receive for processing in plural processing passes, each such processing pass processing a sub-set of the sampling points that the fragment represents, but the fragment shader 6 is configured to process each graphics fragment in a processing pass that processes all the sampling points that the fragment represents in parallel, so as to ensure compliance with the desired higher level of multisampled anti-aliasing.

公开(公告)号：US09772864B2

公开(公告)日：2017-09-26

申请号：US13863599

申请日：2013-04-16

Applicant: ARM Limited

Inventor： Jorn Nystad

IPC: G06F9/445

CPC classification number: G06F9/44521

Abstract: When an OpenCL kernel is to be executed, a bitfield index representation to be used for the indices of the kernel invocations is determined based on the number of bits needed to represent the maximum value that will be needed for each index dimension for the kernel. A bitfield placement data structure 33 describing how the bitfield index representation is partitioned is then prepared together with a maximum value data structure 32 indicating the maximum index dimension values to be used for the kernel. A processor then executes the kernel invocations 36 across the index space indicated by the maximum value data structure 32. A bitfield index representation 35, 37, 38 configured in accordance with the bitfield placement data structure 33 is associated with each kernel invocation to indicate its index.

公开(公告)号：US09524535B2

公开(公告)日：2016-12-20

申请号：US14691572

申请日：2015-04-20

Applicant: ARM LIMITED

Inventor： Jorn Nystad ,  Anders Lassen

IPC: G06T1/20 ,  G06T9/00 ,  H04N19/90 ,  G06T11/00

CPC classification number: G06T1/20 ,  G06T9/00 ,  G06T9/005 ,  G06T11/001 ,  H04N19/90

Abstract: When encoding a texture map 1 for use in graphics processing, the texture map is divided into a plurality of equal-sized blocks 2 of texture data elements. Each block 2 of texture data elements is then encoded as a block of texture data 5 that includes a set of integer values to be used to generate a set of base data values for the block, and a set of index values indicating how to use the base data values to generate data values for the texture data elements that the block represents. The integer values and the index values are both encoded in an encoded texture data block using a combination of base-n values, where n is greater than two, and base-2 values. Predefined bit representations are used to represent plural base-n values (n>2) collectively, and the bits of the bit representations representing the base-n values (n>2) are interleaved with bits representing the base-2 values in the encoded texture data block.

Abstract translation: 当对用于图形处理的纹理图1进行编码时，纹理映射被分成纹理数据元素的多个等大小的块2。 纹理数据元素的每个块2然后被编码为纹理数据块5，该纹理数据块5包括用于生成该块的基本数据值集合的一组整数值，以及一组指示如何使用 基本数据值以生成块表示的纹理数据元素的数据值。 整数值和索引值都使用base-n值（其中n大于2）和base-2值的组合编码在编码纹理数据块中。 预定义位表示用于统一表示多个基n值（n> 2），表示基n值（n> 2）的比特表示的比特与编码的基本n值 纹理数据块。

公开(公告)号：US09489344B2

公开(公告)日：2016-11-08

申请号：US13929599

申请日：2013-06-27

Applicant: ARM Limited

Inventor： Jorn Nystad ,  Sean Tristram Ellis

IPC: G06T1/60 ,  G06F17/17

CPC classification number: G06F17/17

Abstract: A data processor of a processing system, such as a graphics processing system, converts an input data value into an output data value by approximating a function which maps input values to output values. The data processor approximates the function using first and second predetermined ranges of values which are quantized into plural corresponding pairs of range sections, a predetermined gradient for each pair of range sections, and predetermined section end values for each pair of range sections. By using these predetermined parameters, the approximation of the function can be implemented efficiently by the data processor of the processing system.

Abstract translation: 诸如图形处理系统的处理系统的数据处理器通过近似将输入值映射到输出值的函数将输入数据值转换为输出数据值。 数据处理器使用量化为多个对应的范围段对的值的第一和第二预定范围，每对范围段的预定梯度以及每对范围段的预定段结束值来近似该函数。 通过使用这些预定参数，功能的近似可以由处理系统的数据处理器有效地实现。