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71.
公开(公告)号:US11551089B2
公开(公告)日:2023-01-10
申请号:US16836741
申请日:2020-03-31
Applicant: ATI Technologies ULC
Inventor: Mehdi Saeedi , Arash Hariri , Gabor Sines
Abstract: A processing device for executing a machine learning neural network operation includes memory and a processor. The processor is configured to receive input data at a layer of the machine learning neural network operation, receive a plurality of sorted filters to be applied to the input data, apply the plurality of sorted filters to the input data to produce a plurality of different feature maps, compress the plurality of different feature maps according to a sparsity of the feature maps and store the plurality of different feature maps in the memory.
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公开(公告)号:US20220210432A1
公开(公告)日:2022-06-30
申请号:US17135972
申请日:2020-12-28
Applicant: ATI Technologies ULC
Inventor: Feng Pan , Crystal Yeong-Pian Sau , Wei Gao , Mingkai Shao , Dong Liu , Ihab M. A. Amer , Gabor Sines
IPC: H04N19/14 , H04N19/124 , H04N19/196 , H04N19/176
Abstract: A processing apparatus and video encoding method are provided which include receiving a portion of a video sequence and determining complexities for blocks of pixels of the portion of the video sequence. Quantization parameter values for corresponding blocks of pixels are selected based on complexities of the corresponding blocks and visually perceived coding artifacts of the corresponding blocks produced by the quantization parameter values. The blocks of pixels are encoded, using the selected quantization parameter values. The blocks of pixels are decoded and the portion of the video sequence is provided for display.
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公开(公告)号:US20220159286A1
公开(公告)日:2022-05-19
申请号:US17587497
申请日:2022-01-28
Applicant: ATI Technologies ULC
Inventor: Ahmed M. Abdelkhalek , Edward A. Harold , Andy Sung , Stephen Ho , Lei Zhang , Ihab Amer , Gabor Sines , Zhiqi Hao , Yang Liu , Baochun Li , Kai Sun
IPC: H04N19/463 , H04N19/593 , H04N19/152
Abstract: Systems, apparatuses, and methods for reducing latency when consuming an encoded video bitstream in real-time are disclosed. A video encoder encodes a video bitstream and writes chunks of the encoded bitstream to a bitstream buffer. Prior to the encoder completing the encoding of an entire frame, or an entire slice of a frame, a consumer module consumes encoded chunks of the bitstream. In one implementation, to enable pipelining of the consumption with the encoding, the encoder updates a buffer write pointer with an indication of the amount of data that has been written to the bitstream buffer. The consumer module retrieves encoded data from the bitstream buffer up to the location indicated by the buffer write pointer. In this way, the consumer module is able to access and consume encoded video data prior to the encoder finishing encoding an entire frame or an entire slice of the frame.
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公开(公告)号:US11252429B2
公开(公告)日:2022-02-15
申请号:US15965281
申请日:2018-04-27
Applicant: ATI Technologies ULC
Inventor: Ahmed M. Abdelkhalek , Edward A. Harold , Andy Sung , Stephen Ho , Lei Zhang , Ihab Amer , Gabor Sines , Zhiqi Hao , Yang Liu , Baochun Li , Kai Sun
IPC: H04N19/463 , H04N19/593 , H04N19/152
Abstract: Systems, apparatuses, and methods for reducing latency when consuming an encoded video bitstream in real-time are disclosed. A video encoder encodes a video bitstream and writes chunks of the encoded bitstream to a bitstream buffer. Prior to the encoder completing the encoding of an entire frame, or an entire slice of a frame, a consumer module consumes encoded chunks of the bitstream. In one implementation, to enable pipelining of the consumption with the encoding, the encoder updates a buffer write pointer with an indication of the amount of data that has been written to the bitstream buffer. The consumer module retrieves encoded data from the bitstream buffer up to the location indicated by the buffer write pointer. In this way, the consumer module is able to access and consume encoded video data prior to the encoder finishing encoding an entire frame or an entire slice of the frame.
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公开(公告)号:US20210303994A1
公开(公告)日:2021-09-30
申请号:US16836785
申请日:2020-03-31
Applicant: ATI Technologies ULC
Inventor: Arash Hariri , Mehdi Saeedi , Boris Ivanovic , Gabor Sines
Abstract: A processing device for executing a machine learning neural network operation includes memory and a processor. The processor is configured to receive input data at a layer of the machine learning neural network operation, receive a plurality of sorted filters to be applied to the input data, apply the plurality of sorted filters to the input data to produce a plurality of different feature maps, compress the plurality of different feature maps according to a similarity of the feature maps relative to each other and store the plurality of different feature maps in the memory.
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公开(公告)号:US11120289B2
公开(公告)日:2021-09-14
申请号:US16588810
申请日:2019-09-30
Applicant: ATI Technologies ULC
Inventor: Feng Pan , Wei Gao , Yang Liu , Crystal Yeong-Pian Sau , Haibo Liu , Edward A. Harold , Ying Luo , Ihab Amer , Gabor Sines
IPC: G06K9/46 , G06T5/40 , H04N19/423 , H04N19/186 , G06K9/62
Abstract: Systems, apparatuses, and methods for performing parallel histogram calculation with application to palette table derivation are disclosed. An encoder calculates a first histogram for a first portion of pixel component value bits of a block of pixels. Then, the encoder selects a first number of the highest pixel count bins from the first histogram. Also, the encoder calculates a second histogram for a second portion of pixel component value bits of the block. The encoder selects a second number of the highest pixel count bins from the second histogram. A third histogram is calculated from the concatenation of bits assigned to the first and second number of bins, and the highest pixel count bins are selected from the third histogram. A palette table is derived based on these highest pixel count bins selected from the third histogram, and the block of pixels is encoded using the palette table.
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公开(公告)号:US10708624B1
公开(公告)日:2020-07-07
申请号:US16426487
申请日:2019-05-30
Applicant: ATI TECHNOLOGIES ULC
Inventor: Mehdi Saeedi , Boris Ivanovic , Tomasz Stolarczyk , Ihab Amer , Gabor Sines
IPC: H04N19/85 , H04N19/50 , H04N19/182 , H04N19/117 , H04N19/124 , H04N19/176
Abstract: A processing system filters blocks of a picture to minimize a size and error of the blocks prior to encoding. A pre-processing module of the processing system measures characteristics of a plurality of blocks and evaluates the effects of applying each of a plurality of filters to the blocks prior to encoding in order to predict an increase in compressibility of blocks having similar characteristics that are filtered with each filter before being encoded, with the least impact on quality. The pre-processing module trains models to predict a size and error of blocks filtered with each filter based on block characteristics. The pre-processing module uses the models to calculate a cost in terms of size and error of applying each filter to a given block having certain characteristics. The pre-processing module then applies to the block the filter that is predicted to result in the best cost.
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公开(公告)号:US10594901B2
公开(公告)日:2020-03-17
申请号:US15816765
申请日:2017-11-17
Applicant: ATI Technologies ULC
Inventor: Gabor Sines , Kyle Plumadore , Yang Liu , Ihab Amer , Boris Ivanovic
IPC: A63F13/00 , H04N1/60 , H04N19/42 , A63F13/5258 , G06T1/20 , G06T9/00 , A63F13/32 , A63F13/33 , A63F13/335 , A63F13/35
Abstract: Systems, apparatuses, and methods for rendering images directly to a video encoder are disclosed. A game engine includes an embedded rendering unit configured to render images in different color spaces depending on the mode. The rendering unit renders images for a first color space only to be driven directly to a display while operating in a first mode. The rendering unit renders images for a second color space only which are provided directly to a video encoder while operating in a second mode. In a third mode, the rendering unit renders images for both color spaces. In one embodiment, the first color space is RGB and the second color space is YUV. The game engine also generates a plurality of attributes associated with each rendered image and the video encoder encodes each rendered image into an encoded bitstream based on the attributes associated with the rendered image.
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公开(公告)号:US20180349062A1
公开(公告)日:2018-12-06
申请号:US15608370
申请日:2017-05-30
Applicant: ATI Technologies ULC
Inventor: Gabor Sines
CPC classification number: G06F3/0661 , G06F9/485 , G06F9/5016 , G06F17/289 , G06F17/30569
Abstract: Described herein is a method and apparatus for en route translation of data by a data translation logic (DTL) on a solid state graphics (SSG) device as the data moves from a first memory architecture on the SSG device to a second memory architecture associated with a graphics processing units (GPU) on the SSG device or from the first memory architecture on the SSG device to a host memory in a host system that is connected to the SSG device.
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公开(公告)号:US20180063549A1
公开(公告)日:2018-03-01
申请号:US15246503
申请日:2016-08-24
Applicant: ATI Technologies ULC
Inventor: Ihab Amer , Gabor Sines , Jinbo Qiu , Yang Liu , Haibo Liu , Eren Gurses
IPC: H04N19/59 , H04N19/172 , H04N19/126 , H04N19/51 , H04N19/30
CPC classification number: H04N19/59 , H04N19/132 , H04N19/137 , H04N19/172
Abstract: Described is a system and method for dynamically changing a resolution level at a frame level based on runtime pre-encoding analysis of content in a video stream. A video encoder continuously analyzes the content during runtime, and collects statistics and/or characteristics of the content before encoding it. This classifies the frame among pre-defined categories of content, where every category has its own bitrate/resolution relation. The runtime encoding resolution is dynamically dependent on the target bitrate and the collected statistics and/or characteristics of the content. This achieves a high quality encode for sequences that are composed of scenes with various content complexity levels for different frames in the video streams.
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