Wireless access modem having downstream channel resynchronization method
    71.
    发明申请
    Wireless access modem having downstream channel resynchronization method 有权
    具有下行信道重新同步方式的无线接入调制解调器

    公开(公告)号:US20050044472A1

    公开(公告)日:2005-02-24

    申请号:US10643119

    申请日:2003-08-18

    摘要: A resynchronization method for use in a data communication system having a first device configured to transmit data at a symbol rate to a second device. The second device includes a Reed Solomon (RS) decoder having a RS lock indicator and a Moving Picture Experts Group (MPEG) Protocol Interface (MPI) having a MPI lock indicator, wherein the RS and the MPI lock indicators are monitored. Four different states, defined by the values of the RS and MPI lock indicators, determine whether the data communication system will wait for the RS decoder and the MPI hardware block to resynchronize, whether an intermediate-subset of the channel acquisition algorithm is performed or whether the entire channel acquisition algorithm is performed. The method for resynchronization described herein recovers synchronization within a predetermined time without the layers above the physical link layer having knowledge.

    摘要翻译: 一种用于具有第一设备的数据通信系统中的再同步方法,该第一设备被配置为以符号速率向第二设备发送数据。 第二装置包括具有RS锁定指示器的里德所罗门(RS)解码器和具有MPI锁定指示器的运动图像专家组(MPEG)协议接口(MPI),其中监测RS和MPI锁定指示符。 由RS和MPI锁指示符的值定义的四种不同状态确定数据通信系统是否将等待RS解码器和MPI硬件块重新同步,无论是执行信道获取算法的中间子集还是执行 执行整个信道获取算法。 本文所述的用于重新同步的方法在预定时间内恢复同步,而不具有物理链路层之上的层具有知识。

    Performing an iterative bundle adjustment for an imaging device

    公开(公告)号:US10949646B2

    公开(公告)日:2021-03-16

    申请号:US16399519

    申请日:2019-04-30

    摘要: A method of performing an iterative bundle adjustment for an imaging device is described. The method comprising implementing a plurality of functions in performing a bundle adjustment. Predetermined functions of the plurality of functions may be started using a processor for a second iteration in parallel with a first iteration of the plurality of functions. A result of the predetermined functions started during the first iteration may be used in a second iteration. An output of the bundle adjustment may then be generated for successive iterations.

    PERFORMING AN ITERATIVE BUNDLE ADJUSTMENT FOR AN IMAGING DEVICE

    公开(公告)号:US20200349341A1

    公开(公告)日:2020-11-05

    申请号:US16399519

    申请日:2019-04-30

    摘要: A method of performing an iterative bundle adjustment for an imaging device is described. The method comprising implementing a plurality of functions in performing a bundle adjustment. Predetermined functions of the plurality of functions may be started using a processor for a second iteration in parallel with a first iteration of the plurality of functions. A result of the predetermined functions started during the first iteration may be used in a second iteration. An output of the bundle adjustment may then be generated for successive iterations.

    Constant geometry split radix FFT
    74.
    发明授权
    Constant geometry split radix FFT 有权
    恒定几何分裂基数FFT

    公开(公告)号:US08819097B2

    公开(公告)日:2014-08-26

    申请号:US13229470

    申请日:2011-09-09

    IPC分类号: G06F17/10

    CPC分类号: G06F17/142

    摘要: An apparatus for performing a Fast Fourier Transform (FFT) is provided. The apparatus comprises a reorder matrix, symmetrical butterflies, and a memory. The reorder matrix is configured to have a constant geometry, and the butterflies are coupled in parallel to the reorder matrix. The memory is also coupled to the reorder matrix and each butterfly. The reorder matrix, the butterflies, and the memory can then execute a split radix algorithm.

    摘要翻译: 提供了一种用于执行快速傅里叶变换(FFT)的装置。 该装置包括重排序矩阵,对称蝴蝶和存储器。 重新排列矩阵被配置为具有恒定的几何形状,并且蝴蝶与重排序矩阵并联耦合。 存储器也耦合到重新排序矩阵和每个蝴蝶。 然后,重排序矩阵,蝴蝶和存储器可以执行分裂基数算法。

    Security of cryptographic devices against differential power analysis
    75.
    发明授权
    Security of cryptographic devices against differential power analysis 有权
    加密装置对差分功率分析的安全性

    公开(公告)号:US08782446B2

    公开(公告)日:2014-07-15

    申请号:US13353462

    申请日:2012-01-19

    摘要: An embodiment of the invention provides a cryptographic device that draws a substantially constant current from an accessible electrical node that supplies power to the cryptographic device. Keeping the current drawn from the accessible electrical node substantially constant reduces the probability that secure information may be taken by unwanted third parties from the cryptographic device. The cryptographic device includes an active shunt current regulator, a low-pass filter, a linear voltage regulator and an AES (advanced encryption standard) circuit.

    摘要翻译: 本发明的一个实施例提供了一种加密设备,其从可访问的电节点中抽取基本恒定的电流,该电节点向密码设备供电。 保持从可访问的电节点获取的电流基本上是恒定的,降低了不必要的第三方从密码设备获取安全信息的可能性。 密码装置包括主动分流电流调节器,低通滤波器,线性稳压器和AES(高级加密标准)电路。

    Extended bidirectional hamming code for double-error correction and triple-error detection
    76.
    发明授权
    Extended bidirectional hamming code for double-error correction and triple-error detection 有权
    扩展双向汉明码,用于双重纠错和三重检测

    公开(公告)号:US08694872B2

    公开(公告)日:2014-04-08

    申请号:US13305126

    申请日:2011-11-28

    申请人: Manish Goel

    发明人: Manish Goel

    IPC分类号: H03M13/19

    CPC分类号: H03M13/152 H03M13/1575

    摘要: An embodiment of the invention provides a method of correcting 2 bits and detecting three bit using an extended bidirectional Hamming code. A data word with length K=2m−1 is received. A code word with length N=2m−1+2m+1 is generated from the data word in accordance with the extended bidirectional Hamming code defined by the following parity check matrix: H = [ 1 1 … 1 1 α … α N - 1 1 α - 1 … α - N + 1 ] . The number of parity bit is given by (2m+1).

    摘要翻译: 本发明的实施例提供了一种校正2比特并使用扩展双向汉明码检测三比特的方法。 接收长度为K = 2m-1的数据字。 根据由以下奇偶校验矩阵定义的扩展双向汉明码,从数据字产生长度为N = 2m-1 + 2m + 1的码字:H = [1 1 ... 1 1α...αN-1 1α-1 ...α-N + 1]。 奇偶校验位的数量由(2m + 1)给出。

    Interconnect coding method and apparatus
    77.
    发明授权
    Interconnect coding method and apparatus 有权
    互连编码方法和装置

    公开(公告)号:US08571092B2

    公开(公告)日:2013-10-29

    申请号:US13273842

    申请日:2011-10-14

    IPC分类号: H04B1/38

    CPC分类号: G06F1/32 H03M7/42

    摘要: A computer program that is embodied on a storage medium for execution on a processor is provided. With this computer program, A current cost is calculated for each transition on a bus having a predetermined width for a functional circuit so as to form a transition cost matrix. Then, a predetermined number of the lowest cost transitions for from the transition cost matrix is determined so as to generate a probability transition matrix. The product of the probability transition matrix and the transition cost matrix can be iteratively determined, while also updating the probability transition matrix until the probability transition matrix converges.

    摘要翻译: 提供了一种体现在用于在处理器上执行的存储介质上的计算机程序。 利用该计算机程序,为功能电路具有预定宽度的总线上的每个转换计算当前成本,以形成转换成本矩阵。 然后,确定用于从转移成本矩阵的预定数量的最低成本转换,以便生成概率转移矩阵。 可以迭代地确定概率转移矩阵和转移代价矩阵的乘积,同时还更新概率转移矩阵直到概率转移矩阵收敛。

    Extended Bidirectional Hamming Code for Double-Error Correction and Triple-Error Detection
    78.
    发明申请
    Extended Bidirectional Hamming Code for Double-Error Correction and Triple-Error Detection 有权
    用于双误差校正和三重错误检测的扩展双向汉明码

    公开(公告)号:US20130139028A1

    公开(公告)日:2013-05-30

    申请号:US13305126

    申请日:2011-11-28

    申请人: Manish Goel

    发明人: Manish Goel

    IPC分类号: H03M13/00 G06F11/08 H03M13/19

    CPC分类号: H03M13/152 H03M13/1575

    摘要: An embodiment of the invention provides a method of correcting 2 bits and detecting three bit using an extended bidirectional Hamming code. A data word with length K=2m-1 is received. A code word with length N=2m-1+2m+1 is generated from the data word in accordance with the extended bidirectional Hamming code defined by the following parity check matrix: H = [ 1 1 … 1 1 α … α N - 1 1 α - 1 … α - N + 1 ] . The number of parity bit is given by (2m+1).

    摘要翻译: 本发明的实施例提供了一种校正2比特并使用扩展双向汉明码检测三比特的方法。 接收长度为K = 2m-1的数据字。 根据由以下奇偶校验矩阵定义的扩展双向汉明码,从数据字生成长度为N = 2m-1 + 2m + 1的码字:H = [1 1 ... 1 1α... αN -11α-1 ...α-N + 1]。 奇偶校验位的数量由(2m + 1)给出。

    Method, device, and digital circuitry for providing a closed-form solution to a scaled error locator polynomial used in BCH decoding
    79.
    发明授权
    Method, device, and digital circuitry for providing a closed-form solution to a scaled error locator polynomial used in BCH decoding 有权
    用于为BCH解码中使用的缩放误差定位多项式提供封闭形式解的方法,设备和数字电路

    公开(公告)号:US08392806B2

    公开(公告)日:2013-03-05

    申请号:US12846172

    申请日:2010-07-29

    IPC分类号: H03M13/00

    摘要: A method of determining positions of one or more error bits is disclosed. The method includes receiving a BCH codeword at input circuitry of a decoder device, establishing a threshold number of correctable bits, and determining from the received BCH codeword and a root of an encoder polynomial, a value of each of one or more syndromes. The number of the one or more syndromes is twice a maximum number of correctable bits in the received BCH codeword. When the maximum number of correctable bits in the received BCH codeword is less than the threshold number of correctable bits, the value of each coefficient in a scaled error locator polynomial is determined by performing a non-iterative, closed-form solution on the scaled error locator polynomial. The scaled error locator polynomial is an original error locator polynomial scaled by a constant scale factor. The constant scale factor is determined according to the value of each of the one or more syndromes. Having determined the value of each coefficient in the scaled error locator polynomial, one or more roots of the scaled error locator polynomial are obtained. Each of the one or more roots indicates a position of an error bit. A BCH decoder device that can implement the method and a digital circuit that preserves operations implementing the method are also disclosed.

    摘要翻译: 公开了一种确定一个或多个错误位的位置的方法。 该方法包括在解码器装置的输入电路处接收BCH码字,建立阈值数目的可校正比特,以及根据所接收的BCH码字和编码器多项式的根,确定一个或多个综合征中的每一个的值。 一个或多个综合征的数量是接收到的BCH码字中可校正比特的最大数量的两倍。 当接收的BCH码字中的可校正比特的最大数目小于可校正比特的阈值数目时,通过在缩放误差上执行非迭代闭包方法来确定缩放误差定位多项式中的每个系数的值 定位多项式。 缩放误差定位器多项式是通过常数比例因子缩放的原始误差定位器多项式。 恒定比例因子根据一种或多种综合征中的每一种的值确定。 在确定了缩放误差定位多项式中的每个系数的值后,获得了缩放的误差定位多项式的一个或多个根。 一个或多个根中的每一个表示错误位的位置。 还公开了能够实现该方法的BCH解码器装置和保持实现该方法的操作的数字电路。

    Scalable folded decoder architecture for low density parity check codes
    80.
    发明授权
    Scalable folded decoder architecture for low density parity check codes 有权
    用于低密度奇偶校验码的可扩展折叠解码器架构

    公开(公告)号:US08307269B2

    公开(公告)日:2012-11-06

    申请号:US12631455

    申请日:2009-12-04

    IPC分类号: G06F11/00

    摘要: A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable foldable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W=>1.

    摘要翻译: 用于解码具有高子矩阵度的LDPC码的分层消息更新方法和系统具有可扩展的可折叠和灵活的解码器架构,以支持具有非常小的硬件开销和高吞吐量的任意高子矩阵度的LDPC码。 本发明的实施例支持具有子矩阵度数W => 1的LDPC码。