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    Scalable decoder architecture for low density parity check codes
    1.
    发明授权
    Scalable decoder architecture for low density parity check codes 有权
    用于低密度奇偶校验码的可扩展解码器架构

    公开(公告)号：US08307255B2

    公开(公告)日：2012-11-06

    申请号：US12616925

    申请日：2009-11-12

    申请人： Yang Sun ,  Yuming Zhu ,  Manish Goel

    发明人： Yang Sun ,  Yuming Zhu ,  Manish Goel

    IPC分类号： G06F11/00

    CPC分类号： H03M13/114 ,  H03M13/1122 ,  H03M13/6502 ,  H03M13/6505

    摘要： A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W>=1. The architecture does not require duplication of extrinsic memory which greatly reduces decoder complexity. The size of the memory is also independent of sub-matrix degree which makes the decoder scalable for large W values.

    摘要翻译： 用于解码具有高子矩阵度的LDPC码的分层消息更新方法和系统具有可扩展且灵活的解码器架构，以支持具有非常小的硬件开销和高吞吐量的任意高子矩阵度的LDPC码。 本发明的实施例支持子矩阵W> = 1的LDPC码。 该架构不需要外部存储器的重复，这大大降低了解码器的复杂度。 存储器的大小也与子矩阵度无关，这使得解码器可以针对大的W值进行扩展。

    High-speed add-compare-select (ACS) circuit
    2.
    发明授权
    High-speed add-compare-select (ACS) circuit 有权
    高速加法比较选择（ACS）电路

    公开(公告)号：US08205145B2

    公开(公告)日：2012-06-19

    申请号：US12265011

    申请日：2008-11-05

    申请人： Seok-Jun Lee ,  Yuming Zhu ,  Manish Goel

    发明人： Seok-Jun Lee ,  Yuming Zhu ,  Manish Goel

    IPC分类号： H03M13/00

    CPC分类号： G06F7/22 ,  G06F7/544 ,  H03M13/395 ,  H03M13/4107

    摘要： A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional ACS circuit. According to one embodiment of the invention, the path and branch metrics are split into most-significant and least-significant portions, such portions separately added in order to reduce the propagation delay.

    摘要翻译： 用于维特比解码器或turbo解码器的高速加法比较选择（ACS）电路具有比使用传统ACS电路可实现的更低的关键路径延迟。 根据本发明的一个实施例，路径和分支度量被分成最重要和最不重要的部分，这些部分被分开地添加以减少传播延迟。

    High-Speed Add-Compare-Select (ACS) Circuit
    3.
    发明申请
    High-Speed Add-Compare-Select (ACS) Circuit 有权
    高速加法比较选择（ACS）电路

    公开(公告)号：US20090089556A1

    公开(公告)日：2009-04-02

    申请号：US12265011

    申请日：2008-11-05

    申请人： Seok-Jun Lee ,  Yuming Zhu ,  Manish Goel

    发明人： Seok-Jun Lee ,  Yuming Zhu ,  Manish Goel

    IPC分类号： G06F9/305

    CPC分类号： G06F7/22 ,  G06F7/544 ,  H03M13/395 ,  H03M13/4107

    摘要： A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional ACS circuit. According to one embodiment of the invention, the path and branch metrics are split into most-significant and least-significant portions, such portions separately added in order to reduce the propagation delay.

    摘要翻译： 用于维特比解码器或turbo解码器的高速加法比较选择（ACS）电路具有比使用传统ACS电路可实现的更低的关键路径延迟。 根据本发明的一个实施例，路径和分支度量被分成最重要和最不重要的部分，这些部分被分开地添加以减少传播延迟。

    Scalable Decoder Architecture for Low Density Parity Check Codes
    4.
    发明申请
    Scalable Decoder Architecture for Low Density Parity Check Codes 有权
    用于低密度奇偶校验码的可扩展解码器架构

    公开(公告)号：US20100122142A1

    公开(公告)日：2010-05-13

    申请号：US12616925

    申请日：2009-11-12

    申请人： Yang Sun ,  Yuming Zhu ,  Manish Goel

    发明人： Yang Sun ,  Yuming Zhu ,  Manish Goel

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/114 ,  H03M13/1122 ,  H03M13/6502 ,  H03M13/6505

    摘要： A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W>=1. The architecture does not require duplication of extrinsic memory which greatly reduces decoder complexity. The size of the memory is also independent of sub-matrix degree which makes the decoder scalable for large W values.

    摘要翻译： 用于解码具有高子矩阵度的LDPC码的分层消息更新方法和系统具有可扩展且灵活的解码器架构，以支持具有非常小的硬件开销和高吞吐量的任意高子矩阵度的LDPC码。 本发明的实施例支持子矩阵W> = 1的LDPC码。 该架构不需要外部存储器的重复，这大大降低了解码器的复杂度。 存储器的大小也与子矩阵度无关，这使得解码器可以针对大的W值进行扩展。

    Scalable Folded Decoder Architecture for Low Density Parity Check Codes
    5.
    发明申请
    Scalable Folded Decoder Architecture for Low Density Parity Check Codes 有权
    用于低密度奇偶校验码的可扩展折叠解码器架构

    公开(公告)号：US20100115386A1

    公开(公告)日：2010-05-06

    申请号：US12631455

    申请日：2009-12-04

    申请人： Yuming Zhu ,  Manish Goel

    发明人： Yuming Zhu ,  Manish Goel

    IPC分类号： H03M13/09 ,  G06F11/10

    CPC分类号： H03M13/1111 ,  H04L1/0052 ,  H04L1/0057

    摘要： A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable foldable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W=>1.

    摘要翻译： 用于解码具有高子矩阵度的LDPC码的分层消息更新方法和系统具有可扩展的可折叠和灵活的解码器架构，以支持具有非常小的硬件开销和高吞吐量的任意高子矩阵度的LDPC码。 本发明的实施例支持具有子矩阵度数W => 1的LDPC码。

    PARITY CHECK DECODER ARCHITECTURE
    6.
    发明申请
    PARITY CHECK DECODER ARCHITECTURE 有权
    奇妙的检查解码器架构

    公开(公告)号：US20070283215A1

    公开(公告)日：2007-12-06

    申请号：US11744357

    申请日：2007-05-04

    申请人： Yuming Zhu ,  Yanni Chen ,  Dale E. Hocevar ,  Manish Goel

    发明人： Yuming Zhu ,  Yanni Chen ,  Dale E. Hocevar ,  Manish Goel

    IPC分类号： H03M13/00

    CPC分类号： H03M13/1111

    摘要： A method and systems for reducing the complexity of a parity checker are described herein. In at least some preferred embodiments, a parity-check decoder includes column store units and one or more alignment units, which are coupled to the column store units. The column store units outnumber the alignments units.

    摘要翻译： 本文描述了用于降低奇偶校验器的复杂度的方法和系统。 在至少一些优选实施例中，奇偶校验解码器包括列存储单元和耦合到列存储单元的一个或多个对准单元。 列存储单位超出排列单位。

    Performing an iterative bundle adjustment for an imaging device
    7.
    发明授权
    Performing an iterative bundle adjustment for an imaging device 有权

    公开(公告)号：US10949646B2

    公开(公告)日：2021-03-16

    申请号：US16399519

    申请日：2019-04-30

    申请人： Manish Goel ,  Yuming Zhu

    发明人： Manish Goel ,  Yuming Zhu

    IPC分类号： G06K9/00 ,  G06K9/62 ,  G06T7/73 ,  G06T7/579

    摘要： A method of performing an iterative bundle adjustment for an imaging device is described. The method comprising implementing a plurality of functions in performing a bundle adjustment. Predetermined functions of the plurality of functions may be started using a processor for a second iteration in parallel with a first iteration of the plurality of functions. A result of the predetermined functions started during the first iteration may be used in a second iteration. An output of the bundle adjustment may then be generated for successive iterations.

    PERFORMING AN ITERATIVE BUNDLE ADJUSTMENT FOR AN IMAGING DEVICE
    8.
    发明申请
    PERFORMING AN ITERATIVE BUNDLE ADJUSTMENT FOR AN IMAGING DEVICE 审中-公开

    公开(公告)号：US20200349341A1

    公开(公告)日：2020-11-05

    申请号：US16399519

    申请日：2019-04-30

    申请人： Manish Goel ,  Yuming Zhu

    发明人： Manish Goel ,  Yuming Zhu

    IPC分类号： G06K9/00 ,  G06K9/62 ,  G06T7/579 ,  G06T7/73

    摘要： A method of performing an iterative bundle adjustment for an imaging device is described. The method comprising implementing a plurality of functions in performing a bundle adjustment. Predetermined functions of the plurality of functions may be started using a processor for a second iteration in parallel with a first iteration of the plurality of functions. A result of the predetermined functions started during the first iteration may be used in a second iteration. An output of the bundle adjustment may then be generated for successive iterations.

    Scalable folded decoder architecture for low density parity check codes
    9.
    发明授权
    Scalable folded decoder architecture for low density parity check codes 有权
    用于低密度奇偶校验码的可扩展折叠解码器架构

    公开(公告)号：US08307269B2

    公开(公告)日：2012-11-06

    申请号：US12631455

    申请日：2009-12-04

    申请人： Yuming Zhu ,  Manish Goel

    发明人： Yuming Zhu ,  Manish Goel

    IPC分类号： G06F11/00

    CPC分类号： H03M13/1111 ,  H04L1/0052 ,  H04L1/0057

    摘要： A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable foldable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W=>1.

    摘要翻译： 用于解码具有高子矩阵度的LDPC码的分层消息更新方法和系统具有可扩展的可折叠和灵活的解码器架构，以支持具有非常小的硬件开销和高吞吐量的任意高子矩阵度的LDPC码。 本发明的实施例支持具有子矩阵度数W => 1的LDPC码。

    Parity check decoder architecture
    10.
    发明授权
    Parity check decoder architecture 有权
    奇偶校验解码器架构

    公开(公告)号：US07945838B2

    公开(公告)日：2011-05-17

    申请号：US11744357

    申请日：2007-05-04

    申请人： Yuming Zhu ,  Yanni Chen ,  Dale E. Hocevar ,  Manish Goel

    发明人： Yuming Zhu ,  Yanni Chen ,  Dale E. Hocevar ,  Manish Goel

    IPC分类号： H03M13/00

    CPC分类号： H03M13/1111

    摘要： A method and systems for reducing the complexity of a parity checker are described herein. In at least some preferred embodiments, a parity-check decoder includes column store units and one or more alignment units, which are coupled to the column store units. The column store units outnumber the alignments units.

    摘要翻译： 本文描述了用于降低奇偶校验器的复杂度的方法和系统。 在至少一些优选实施例中，奇偶校验解码器包括列存储单元和耦合到列存储单元的一个或多个对准单元。 列存储单位超出排列单位。