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    Display with shallow contact holes and reduced metal residue at planarization layer steps
    71.
    发明授权
    Display with shallow contact holes and reduced metal residue at planarization layer steps 有权

    公开(公告)号：US10101853B2

    公开(公告)日：2018-10-16

    申请号：US15260137

    申请日：2016-09-08

    Applicant: Apple Inc.

    Inventor： Yu Cheng Chen ,  Keitaro Yamashita ,  Abbas Jamshidi Roudbari ,  Hirokazu Yamagata ,  Ting-Kuo Chang

    IPC: H01L27/12 ,  G06F3/041 ,  G06F3/044

    Abstract: Thin-film transistor circuitry for a display may include conductive layers such as transparent conductive layers and metal layers and may include dielectric layers. The dielectric layers may include buffer layers, interlayer dielectric, gate insulator, and organic planarization layers. The organic planarization layers may be patterned photolithographically to form vias, trenches, and other structures. Trenches may be formed by removing the planarization layer in a strip. When planarization material is removed for forming a trench or other structure, a step is formed in the planarization material. Metal lines such as data lines and other signal lines may cross steps in the planarization material. To prevent shorts between lines, a step may have protrusions that help eliminate metal etch residue. Vias may be reduced in depth by forming metal bumps and dielectric bumps under the vias and by forming other via structures.

    Different lightly doped drain length control for self-align light drain doping process
    78.
    发明授权
    Different lightly doped drain length control for self-align light drain doping process 有权

    公开(公告)号：US09685557B2

    公开(公告)日：2017-06-20

    申请号：US13801261

    申请日：2013-03-13

    Applicant: APPLE INC.

    Inventor： Cheng-Ho Yu ,  Young Bae Park ,  Shih Chang Chang ,  Ting-Kuo Chang ,  Shang-Chih Lin

    IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12

    CPC classification number: H01L29/78651 ,  H01L27/1288 ,  H01L29/6675 ,  H01L29/78621 ,  H01L29/78645

    Abstract: A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack. The TFT stack includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes removing the first photoresist layer, and depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area. The method further includes doping the second portion of the doped semiconductor layer with a third doping dose, the first dose being higher than the second dose and the third dose.

    Low complexity gate line driver circuitry
    80.
    发明授权
    Low complexity gate line driver circuitry 有权
    低复杂度的栅极线驱动电路

    公开(公告)号：US09317151B2

    公开(公告)日：2016-04-19

    申请号：US13747872

    申请日：2013-01-23

    Applicant: Apple Inc.

    Inventor： Abbas Jamshidi-Roudbari ,  Cheng-Ho Yu ,  Shih Chang Chang ,  Ting-Kuo Chang

    IPC: G06F3/041 ,  G06F3/044

    CPC classification number: G06F3/0412 ,  G06F3/0416 ,  G06F3/044

    Abstract: Gate driver circuitry that controls an array of display elements is described. The gate driver circuitry has gate drivers that apply a control pulse to each of a number of gate lines in sequence, from a previous gate line to a current gate line, during a frame interval in which the array of display elements is filled with pixel values. Each gate driver has a latch stage followed by an output stage. The output stage is coupled to drive a current gate line, and the latch stage is coupled to drive a) a first hold circuit that holds the current gate line at a predetermined voltage, and b) a second hold circuit that holds a previous gate line at a predetermined voltage. Other embodiments are also described and claimed.

    Abstract translation: 描述了控制显示元件阵列的栅极驱动器电路。 栅极驱动器电路具有栅极驱动器，该栅极驱动器在其中显示元件阵列被填充有像素值的帧间隔期间，将序列中的每一条栅极线上的控制脉冲从先前的栅极线施加到当前栅极线 。 每个门驱动器都有一个锁存级，后跟一个输出级。 输出级耦合以驱动电流栅极线，并且锁存级耦合以驱动a）将电流栅极线保持在预定电压的第一保持电路，以及b）保持先前栅极线的第二保持电路 在预定电压下。 还描述和要求保护其他实施例。

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