公开(公告)号：US11631439B1

公开(公告)日：2023-04-18

申请号：US17515258

申请日：2021-10-29

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Munish Kumar ,  Andy Wangkun Chen ,  Rajiv Kumar Sisodia

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C5/06

Abstract: Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.

公开(公告)号：US20220343970A1

公开(公告)日：2022-10-27

申请号：US17238683

申请日：2021-04-23

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Andy Wangkun Chen

IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4094 ,  G11C5/06

Abstract: Various implementations described herein are directed to a device having a multi-tiered memory structure with a first tier and a second tier arranged vertically in a stacked configuration. The device may have multiple transistors disposed in the multi-tiered memory structure with first transistors disposed in the first tier and second transistors disposed in the second tier. The device may have a single interconnect that vertically couples the first transistors in the first tier to the second transistors in the second tier.

公开(公告)号：US11468941B2

公开(公告)日：2022-10-11

申请号：US17193632

申请日：2021-03-05

Applicant: Arm Limited

Inventor： Akash Bangalore Srinivasa ,  Andy Wangkun Chen ,  Penaka Phani Goberu ,  Yew Keong Chong

IPC: G11C11/4074 ,  G11C5/06 ,  G11C11/4093 ,  G11C5/14 ,  G11C11/4094 ,  G11C11/4076 ,  H03K19/017

Abstract: Various implementations described herein are related to a device having memory circuitry with an array of bitcells coupled to a power rail. The device may have pulse-bias circuitry with stacks of transistors that are coupled to the power rail. In various instances, the stacks of transistors may be alternately activated so as to thereby provide a pulse-biased power supply to the array of bitcells via the power rail.

公开(公告)号：US20220284942A1

公开(公告)日：2022-09-08

申请号：US17193632

申请日：2021-03-05

Applicant: Arm Limited

Inventor： Akash Bangalore Srinivasa ,  Andy Wangkun Chen ,  Penaka Phani Goberu ,  Yew Keong Chong

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4093 ,  G11C5/06 ,  G11C5/14 ,  H03K19/017

Abstract: Various implementations described herein are related to a device having memory circuitry with an array of bitcells coupled to a power rail. The device may have pulse-bias circuitry with stacks of transistors that are coupled to the power rail. In various instances, the stacks of transistors may be alternately activated so as to thereby provide a pulse-biased power supply to the array of bitcells via the power rail.

公开(公告)号：US20220123751A1

公开(公告)日：2022-04-21

申请号：US17076549

申请日：2020-10-21

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Andy Wangkun Chen ,  Ayush Kulshrestha ,  Sony ,  Rajiv Kumar Sisodia

IPC: H03K19/00 ,  G11C11/417

Abstract: Various implementations described herein are related to a device having logic that operates in multiple voltage domains. The device may include a backside power network with rows of segmented supply rails coupled to the logic. The rows of segmented supply rails may include alternating rail breaks that define an interchanging directional supply of power to the logic in the multiple voltage domains.

公开(公告)号：US20220122656A1

公开(公告)日：2022-04-21

申请号：US17076540

申请日：2020-10-21

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Andy Wangkun Chen ,  Ayush Kulshrestha ,  Sony ,  Sriram Thyagarajan ,  Yew Keong Chong

IPC: G11C11/418

Abstract: Various implementations described herein are related to a device having wordline drivers coupled to a core array. The device may have backside power network with buried power rails. The device may have header logic coupled to power supply connections of the wordline drivers by way of the buried power rails, and the header logic may be used to power-gate the wordline drivers.

公开(公告)号：US11288432B2

公开(公告)日：2022-03-29

申请号：US17062567

申请日：2020-10-03

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Gus Yeung ,  Marlin Wayne Frederick, Jr. ,  Sriram Thyagarajan

IPC: G06F30/39 ,  G06F30/30 ,  G06F30/398 ,  G06F30/392 ,  G06F30/394

Abstract: Various implementations described herein are directed to a method. The method may provide a tile database with multiple tiles that define one or more first component sections for a memory device. The method may define an array of storage elements having a specified memory array width. The method may define one or more second component sections having at least part of a standard cell based tile with standard cells arranged in multiple standard cell rows. The method may generate a memory instance by defining a layout for the memory device with the multiple tiles selected from the tile database based on matching the multiple standard cell rows to the specified memory array width of the array of storage elements.

公开(公告)号：US20220084561A1

公开(公告)日：2022-03-17

申请号：US17019030

申请日：2020-09-11

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony N/A ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: G11C5/14 ,  G11C8/08

Abstract: Various implementations described herein refer to a device having backside power rails including first backside power rails that supply a core voltage to memory logic and second backside power rails that supply a periphery voltage to control logic. In some implementations, at least one first backside power rail may have a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic.

公开(公告)号：US20220077857A1

公开(公告)日：2022-03-10

申请号：US17013199

申请日：2020-09-04

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: H03K19/17736 ,  H03K19/1776

Abstract: Various implementations described herein are related to a device with a frontside power network and a backside power network. The frontside power network may include frontside supply rails coupled to logic circuitry, and also, the backside power network may include buried supply rails. Also, at least one buried supply rail of the buried supply rails may be used as a backside signal path for providing at least one critical signal net to the logic circuitry.

公开(公告)号：US20220074988A1

公开(公告)日：2022-03-10

申请号：US17013628

申请日：2020-09-06

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Frank David Frederick ,  Richard Slobodnik

IPC: G01R31/3177 ,  G11C11/419 ,  G01R31/317

Abstract: A memory circuit includes input multiplexers passing one of a pair of input bits. A first input multiplexer receives a first data bit and a serial input bit. Additional input multiplexers receive either a respective pair of data (D) bits, or a write-enable (WEN) bit and a single D bit. Scan latches receive one of the input bits and provide a scan output bit. OR gates arranged receive the scan output bit from a different scan latch, and perform a logical OR operation thereon to generate an OR output bit. Downstream output multiplexers pass a corresponding bit from a bit array or the OR output bit from a corresponding OR gate, and sense latches receive the corresponding bit from one of the output multiplexers and provide a sense output bit. Each sense output bit feeds into one or more input multiplexers when a bit-write-mask function is disabled.