公开(公告)号：US11315654B2

公开(公告)日：2022-04-26

申请号：US16151220

申请日：2018-10-03

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yannis Jallamion-Grive ,  Cyrille Nicolas Dray ,  Frank David Frederick

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/52 ,  G11C29/14 ,  G11C29/04 ,  G11C29/00

Abstract: Various implementations described herein refer to an integrated circuit having first circuitry and second circuitry. The first circuitry receives first input data and bypasses error correction circuitry to determine whether the first input data has one or more first errors. The second circuitry receives second input data and enables the error correction circuitry to determine whether the second input data has one or more second errors.

公开(公告)号：US11280832B1

公开(公告)日：2022-03-22

申请号：US17013628

申请日：2020-09-06

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Frank David Frederick ,  Richard Slobodnik

IPC: G01R31/3177 ,  G11C11/419 ,  G01R31/317 ,  G11C11/409 ,  H03K19/20

Abstract: A memory circuit includes input multiplexers passing one of a pair of input bits. A first input multiplexer receives a first data bit and a serial input bit. Additional input multiplexers receive either a respective pair of data (D) bits, or a write-enable (WEN) bit and a single D bit. Scan latches receive one of the input bits and provide a scan output bit. OR gates arranged receive the scan output bit from a different scan latch, and perform a logical OR operation thereon to generate an OR output bit. Downstream output multiplexers pass a corresponding bit from a bit array or the OR output bit from a corresponding OR gate, and sense latches receive the corresponding bit from one of the output multiplexers and provide a sense output bit. Each sense output bit feeds into one or more input multiplexers when a bit-write-mask function is disabled.

公开(公告)号：US20180156866A1

公开(公告)日：2018-06-07

申请号：US15368480

申请日：2016-12-02

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Teresa Louise Mclaurin ,  Richard Slobodnik ,  Frank David Frederick ,  Kartikey Jani

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318583 ,  G11C2029/3202

Abstract: Various implementations described herein are directed to a scan cell. The scan cell may include an input phase having multiple multiplexers and a latch arranged to receive a scan input signal, a first address signal, and a second address signal and provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a selection enable signal. The scan cell may include an output phase having multiple latches arranged to receive the scan input signal, the first address signal, or the second address signal from the input phase and provide the scan input signal, the first address signal, or the second address signal as a scan output signal based on a second clock signal and a third clock signal.

公开(公告)号：US20220074988A1

公开(公告)日：2022-03-10

申请号：US17013628

申请日：2020-09-06

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Frank David Frederick ,  Richard Slobodnik

IPC: G01R31/3177 ,  G11C11/419 ,  G01R31/317

Abstract: A memory circuit includes input multiplexers passing one of a pair of input bits. A first input multiplexer receives a first data bit and a serial input bit. Additional input multiplexers receive either a respective pair of data (D) bits, or a write-enable (WEN) bit and a single D bit. Scan latches receive one of the input bits and provide a scan output bit. OR gates arranged receive the scan output bit from a different scan latch, and perform a logical OR operation thereon to generate an OR output bit. Downstream output multiplexers pass a corresponding bit from a bit array or the OR output bit from a corresponding OR gate, and sense latches receive the corresponding bit from one of the output multiplexers and provide a sense output bit. Each sense output bit feeds into one or more input multiplexers when a bit-write-mask function is disabled.

公开(公告)号：US20210074353A1

公开(公告)日：2021-03-11

申请号：US17101610

申请日：2020-11-23

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Teresa Louise McLaurin ,  Frank David Frederick ,  Richard Slobodnik ,  Yew Keong Chong

IPC: G11C11/419 ,  G11C7/22 ,  H03K19/1776 ,  G11C7/10

Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.

公开(公告)号：US20190325947A1

公开(公告)日：2019-10-24

申请号：US15956724

申请日：2018-04-18

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Teresa Louise McLaurin ,  Frank David Frederick ,  Richard Slobodnik ,  Yew Keong Chong

IPC: G11C11/419 ,  G11C7/22 ,  G11C7/10 ,  H03K19/177

Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.

公开(公告)号：US11568926B2

公开(公告)日：2023-01-31

申请号：US17101610

申请日：2020-11-23

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Teresa Louise McLaurin ,  Frank David Frederick ,  Richard Slobodnik ,  Yew Keong Chong

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/22 ,  H03K19/1776 ,  G11C7/10

Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.

公开(公告)号：US10222418B2

公开(公告)日：2019-03-05

申请号：US15368480

申请日：2016-12-02

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Teresa Louise Mclaurin ,  Richard Slobodnik ,  Frank David Frederick ,  Kartikey Jani

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  G11C29/32

Abstract: Various implementations described herein are directed to a scan cell. The scan cell may include an input phase having multiple multiplexers and a latch arranged to receive a scan input signal, a first address signal, and a second address signal and provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a selection enable signal. The scan cell may include an output phase having multiple latches arranged to receive the scan input signal, the first address signal, or the second address signal from the input phase and provide the scan input signal, the first address signal, or the second address signal as a scan output signal based on a second clock signal and a third clock signal.