公开(公告)号：US06988255B2

公开(公告)日：2006-01-17

申请号：US10667083

申请日：2003-09-18

申请人： Robert J. Allen ,  Ravishankar Arunachalam ,  David J. Hathaway

发明人： Robert J. Allen ,  Ravishankar Arunachalam ,  David J. Hathaway

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and structure to determine timing windows in a static timing analysis of an integrated circuit design, determines for at least one node in the integrated circuit design, an initial set of sub-windows and merges the sub-windows of the initial set into a final set of sub-windows.

公开(公告)号：US06985004B2

公开(公告)日：2006-01-10

申请号：US09781369

申请日：2001-02-12

申请人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： H03K17/16

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

公开(公告)号：US06711719B2

公开(公告)日：2004-03-23

申请号：US09928573

申请日：2001-08-13

申请人： John Maxwell Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas Michael Lepsic ,  Patrick Edward Perry ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： John Maxwell Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas Michael Lepsic ,  Patrick Edward Perry ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： G06F1750

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.

摘要翻译： 在集成电路（IC）设计中，功率消耗的分量可以表示为功率=½FCV <2>，其中C是由源单元驱动的负载电容，F是源单元的开关频率，V 是总输出电压摆幅。 然而，不是由源单元产生的每个信号值都不需要传播到芯片的每个时钟周期连接到源的所有宿单元。 因此，将隔离单元插入到将源单元连接到至少一个宿单元的网络（有线）中，以便当由所述源单元输出的信号从所述源单元输出时，将所述至少一个宿单元和所述网的一部分与所述源单元分离 源不需要传播。 由于去耦合，与至少一个接收器和净部分相关联的负载电容对于这种信号不被源单元体验。 因此，整体IC功耗降低。

公开(公告)号：US5535145A

公开(公告)日：1996-07-09

申请号：US383338

申请日：1995-02-03

申请人： David J. Hathaway

发明人： David J. Hathaway

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An abstracted delay model for a circuit network is generated wherein each internal node and connecting edges of an inputted detailed delay graph are processed. All delay edges in the delay graph which could contribute to an extreme delay path from some primary input of the delay graph are marked as necessary. Unnecessary edges are then removed to produce a partially abstracted delay graph. For each internal node in the partially abstracted delay graph, in-edges and out-edges of the node are then merged, if merging does not cause an increase in the number of edges in the delay graph, thus reducing the total number of edges in the delay abstraction.

摘要翻译： 生成电路网络的抽象延迟模型，其中处理输入的详细延迟图的每个内部节点和连接边缘。 延迟图中的所有可能有助于延迟图形的主要输入端的延迟路径的延迟边被标记为必要。 然后移除不必要的边以产生部分抽象的延迟图。 对于部分抽象的延迟图中的每个内部节点，节点的边缘和边缘然后合并，如果合并不会导致延迟图中边缘数量的增加，从而减少边缘总数 延迟抽象。

公开(公告)号：US5339253A

公开(公告)日：1994-08-16

申请号：US715178

申请日：1991-06-14

申请人： Keith M. Carrig ,  David J. Hathaway ,  Keith W. Lallier ,  Jeannie T. H. Panner ,  Terrence W. Sehr

发明人： Keith M. Carrig ,  David J. Hathaway ,  Keith W. Lallier ,  Jeannie T. H. Panner ,  Terrence W. Sehr

IPC分类号： G06F1/10 ,  G06F17/50 ,  G06F15/60

CPC分类号： G06F17/5077 ,  G06F1/10

摘要： A signal distribution tree is constructed from the leaves to the root by pairing sinks having similar locations, latency requirements and generating function requirements, then determining the minimum cost route or routes between paired sinks, establishing at least one drive point for each minimum cost path which drive point will satisfy the latency requirements for the pair of sinks it serves and then treating each resulting set of drive points as a new sink to be paired while removing the initial sinks from the list of sinks to be paired, continuing this process iteratively until a single set of drive points results and, finally, connecting the signal source to one of the drive points in the final set.

摘要翻译： 通过配对具有相似位置，等待时间要求和生成功能需求的汇，然后确定配对接收器之间的最小成本路由或路由，为每个最小成本路径建立至少一个驱动点，从信号分配树构建信号分配树， 驱动点将满足其所服务的一对接收器的延迟要求，然后将每个所得到的驱动点集合作为待配对的新的接收器，同时从要配对的接收器列表中移除初始接收器，继续迭代过程直到 单个驱动点的结果，最后，将信号源连接到最终设置中的一个驱动点。

公开(公告)号：US4916627A

公开(公告)日：1990-04-10

申请号：US127323

申请日：1987-12-02

申请人： David J. Hathaway

发明人： David J. Hathaway

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： An apparatus and method for reducing the number of gate levels of a logic network. The gates of the network are levelized in a forward and backward direction to determine the worst path length of the network. A gate in the worst path is selected in accordance with a specified scoring function. A local Boolean compression is applied to the selected gate, thereby reducing the number of gate levels of the logic network.

公开(公告)号：US3948423A

公开(公告)日：1976-04-06

申请号：US478861

申请日：1974-06-13

申请人： David J. Hathaway

发明人： David J. Hathaway

IPC分类号： F41C33/00

CPC分类号： F41C33/002 ,  F41C33/001

摘要： An auxiliary gun sling, mountable to a rifle or shotgun, is utilized in combination with a conventional gun sling to securely hold a rifle or shotgun to the user's body when the weapon is not in use, and to facilitate a firm grip on the weapon as it is being fired. The sling is comprised of an elongated elastically extensible resilient strap having snap clips at either end for releasably mounting the strap to the front and back sling swivels of a rifle or shotgun. The auxiliary sling assures the user free use of both hands while carrying the weapon and facilitates quick and smooth movement of the weaponn from a carrying position to a firing position. At the firing position the tension of the resilient strap serves to hold the weapon firmly against the user's shoulder. The strap acts in conjunction with the conventional sling to firmly position the rifle barrel by bracing the user's rifle-supporting arm.

摘要翻译： 一个可以安装到步枪或霰弹枪上的辅助枪吊带与常规的枪支组合使用，以便在武器不使用时将步枪或霰弹枪牢固地固定在使用者的身上，并且有助于牢固地抓住武器。 它正在被解雇。 吊带由细长的弹性可伸展的弹性带组成，弹性带在任一端具有卡扣夹，用于可释放地将吊带安装在步枪或霰弹枪的前后吊索上。 辅助吊带确保使用者在携带武器时自由使用双手，并且便于将武器从携带位置快速平稳地移动到击发位置。 在发射位置，弹性带的张力用于将武器牢固地固定在用户的肩上。 绑带与常规吊带结合起来，通过支撑使用者的步枪支撑臂来牢固地定位步枪枪管。

公开(公告)号：US08776004B2

公开(公告)日：2014-07-08

申请号：US13006450

申请日：2011-01-14

申请人： Frank Borkam ,  Hemlata Gupta ,  David J. Hathaway ,  Kerim Kalafala ,  Vasant Rao ,  Alex Rubin

发明人： Frank Borkam ,  Hemlata Gupta ,  David J. Hathaway ,  Kerim Kalafala ,  Vasant Rao ,  Alex Rubin

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.

摘要翻译： 使用反向合并定时确定时钟整形和其他数字电路的非控制输入端的静态时序分析余量包括：在逻辑设计中选择一个或多个具有多个输入并使用反向合并的电路; 从所述多个输入中识别所选择的电路的控制输入; 以及为所述电路的至少一个非控制输入确定可基于所述控制和非控制输入的到达时间之间的差异来驱动设计优化的定时值。

公开(公告)号：US20120311515A1

公开(公告)日：2012-12-06

申请号：US13151295

申请日：2011-06-02

申请人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

发明人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

IPC分类号： G06F9/455

CPC分类号： G06F17/5031 ,  G06F8/20 ,  G06F2217/84

摘要： A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task. As all data structures of each child thread are accessed only by the child thread owing them, no access locks are required for construction and processing of thread specific graph replica of the timing sub-graph. The construction of each thread specific graph replica is performed by the child thread without locking the main timing graph data structures. Access locks are used only for transferring results of the analysis back to the main timing graph where the results computed by all child threads are combined together.

摘要翻译： 描述了一种用于定时图的有效多线程分析的方法。 该方法适用于多线程公共路径悲观消除，定时报告生成的关键路径遍历以及需要遍历时序图子图的其他类型分析。 为了实现并行多线程执行的高效率和可扩展性，访问锁的数量最小化。 使用一个父计算线程和多个子线程。 父计算线程识别用于分析的任务，并在子线程之间分配它们。 每个子线程标识要分析的子图，创建所识别的子图的线程特定副本，并执行所需的分析。 完成分析后，子线程将结果传回主时序图，等待下一个任务。 由于每个子线程的所有数据结构仅由它们的子线程访问，所以不需要访问锁来构建和处理定时子图的线程特定图形副本。 每个线程特定图形副本的构造由子线程执行，而不锁定主时序图数据结构。 访问锁仅用于将分析结果传回主时序图，其中所有子线程计算的结果组合在一起。

公开(公告)号：US20120185810A1

公开(公告)日：2012-07-19

申请号：US13006450

申请日：2011-01-14

申请人： Frank Borkam ,  Hemlata Gupta ,  David J. Hathaway ,  Kerim Kalafala ,  Vasant Rao ,  Alex Rubin

发明人： Frank Borkam ,  Hemlata Gupta ,  David J. Hathaway ,  Kerim Kalafala ,  Vasant Rao ,  Alex Rubin

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.

摘要翻译： 使用反向合并定时确定时钟整形和其他数字电路的非控制输入端的静态时序分析余量包括：在逻辑设计中选择一个或多个具有多个输入并使用反向合并的电路; 从所述多个输入中识别所选择的电路的控制输入; 以及为所述电路的至少一个非控制输入确定可基于所述控制和非控制输入的到达时间之间的差异来驱动设计优化的定时值。