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    Scheduler, network processor, and methods for weighted best effort scheduling
    73.
    发明授权
    Scheduler, network processor, and methods for weighted best effort scheduling 失效
    调度器，网络处理器和加权最佳努力调度的方法

    公开(公告)号：US07529224B2

    公开(公告)日：2009-05-05

    申请号：US11108485

    申请日：2005-04-18

    申请人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Jean Verplanken

    发明人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Jean Verplanken

    IPC分类号： H04L12/28

    CPC分类号： H04L47/568 ,  H04L45/00 ,  H04L45/60 ,  H04L47/50 ,  H04L47/527

    摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a three-entry calendar structure provides for weighted best effort scheduling. Each of a plurality different flows has an associated schedule control block. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a weight according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its weight, the schedule control block is temporarily removed from further scheduling.

    摘要翻译： 公开了一种用于在网络处理器中调度数据分组的系统和方法。 实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。 在一个实施例中，三入口日历结构提供加权最佳努力调度。 多个不同的流中的每一个具有相关的进度控制块。 计划控制块作为链表存储在先进先出缓冲区中。 通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。 每个调度控制块具有计数器，并根据相应分组所属的流的带宽优先级分配权重。 每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。 当调度控制块的递增计数器等于其权重时，调度控制块暂时从进一步调度中移除。

    Sequence-preserving deep-packet processing in a multiprocessor system
    75.
    发明授权
    Sequence-preserving deep-packet processing in a multiprocessor system 失效
    在多处理器系统中对序列进行深度包处理

    公开(公告)号：US07499470B2

    公开(公告)日：2009-03-03

    申请号：US11963898

    申请日：2007-12-24

    申请人： Jean Louis Calvignac ,  Mohammad Pevravian ,  Fabrice Jean Verplanken

    发明人： Jean Louis Calvignac ,  Mohammad Pevravian ,  Fabrice Jean Verplanken

    IPC分类号： H04J3/24

    CPC分类号： H04L49/9094 ,  H04L47/10 ,  H04L47/34 ,  H04L49/90 ,  H04L49/9089

    摘要： Packets or frames of data may be compressed, encrypted/decrypted, filtered, classified, searched or subjected to other deep-packet processing operations before being distributed through the internet. The microprocessor system and method of the present invention provide for the orderly processing of such data packets without disrupting or changing the sequence in which the data is intended to be transmitted to its destination. This is achieved by receiving frames into an input buffer for processing. Associated with this input buffer is a unit for determining the operation to be performed on each frame. An arbitrator assigns each frame to a processing core engine. An output buffer collects the processed frames, and a sequencer forwards the processed frames from the output buffer to their destination in the same order as received by the input/output buffer. Maintaining the sequence of data transmission is particularly useful in voice transmission, such as videos and movies.

    摘要翻译： 数据包或数据帧可以在通过互联网分发之前被压缩，加密/解密，过滤，分类，搜索或经受其他深度包处理操作。 本发明的微处理器系统和方法提供这种数据分组的有序处理，而不会中断或改变数据要发送到其目的地的序列。 这通过将帧接收到用于处理的输入缓冲器中来实现。 与该输入缓冲器相关联的是用于确定要在每个帧上执行的操作的单元。 仲裁员将每个帧分配给处理核心引擎。 输出缓冲器收集经处理的帧，并且定序器按照输入/输出缓冲器接收的顺序将处理后的帧从输出缓冲区转发到其目的地。 保持数据传输的顺序在诸如视频和电影的语音传输中特别有用。

    Systems and methods for implementing counters in a network processor with cost effective memory
    77.
    发明授权
    Systems and methods for implementing counters in a network processor with cost effective memory 失效
    在具有成本效益的存储器的网络处理器中实现计数器的系统和方法

    公开(公告)号：US07293158B2

    公开(公告)日：2007-11-06

    申请号：US11070060

    申请日：2005-03-02

    申请人： Jean Louis Calvignac ,  Chih-jen Chang ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    发明人： Jean Louis Calvignac ,  Chih-jen Chang ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    IPC分类号： G06F15/00 ,  G06F12/00

    CPC分类号： H04L49/901 ,  H04L49/90

    摘要： Systems and methods for implementing counters in a network processor with cost effective memory are disclosed. Embodiments include systems and methods for implementing counters in a network processor using less expensive memory such as DRAM. A network processor receives packets and implements accounting functions including counting packets in each of a plurality of flow queues. Embodiments include a counter controller that may increment counter values more than once during a R-M-W cycle. Each time a counter controller receives a request to update a counter during a R-M-W cycle that has been initiated for the counter, the counter controller increments the counter value received from memory. The incremented value is written to memory during the write cycle of the R-M-W cycle. A write disable unit disables writes that would otherwise occur during R-M-W cycles initiated for the counter during the earlier initiated R-M-W cycle.

    摘要翻译： 公开了在具有成本效益的存储器的网络处理器中实现计数器的系统和方法。 实施例包括用于在使用诸如DRAM的廉价存储器的网络处理器中实现计数器的系统和方法。 网络处理器接收分组并实现计费功能，包括在多个流队列中的每一个中计数分组。 实施例包括可以在R-M-W周期期间多次增加计数器值的计数器控制器。 每当计数器控制器在已经为计数器启动的R-M-W周期期间接收到更新计数器的请求时，计数器控制器递增从存储器接收的计数器值。 在R-M-W周期的写周期期间，递增的值被写入存储器。 写禁止单元禁用在较早启动的R-M-W周期期间为计数器启动的R-M-W周期期间将发生的写入。

    STM-1 to STM-64 SDH/SONET framer with data multiplexing from a series of configurable I/O ports
    78.
    发明授权
    STM-1 to STM-64 SDH/SONET framer with data multiplexing from a series of configurable I/O ports 失效
    STM-1至STM-64 SDH / SONET成帧器，具有来自一系列可配置I / O端口的数据复用功能

    公开(公告)号：US07161961B2

    公开(公告)日：2007-01-09

    申请号：US09880450

    申请日：2001-06-13

    申请人： Kenneth James Barker ,  Rolf Clauberg ,  Jean Louis Calvignac ,  Andreas Guenther Herkersdorf ,  Fabrice Jean Verplanken ,  David John Webb

    发明人： Kenneth James Barker ,  Rolf Clauberg ,  Jean Louis Calvignac ,  Andreas Guenther Herkersdorf ,  Fabrice Jean Verplanken ,  David John Webb

    IPC分类号： H04J3/00 ,  H04J3/02 ,  H04L12/56

    CPC分类号： H04J3/1611 ,  H04J3/0685 ,  H04J3/22 ,  H04J2203/0089

    摘要： The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.

    摘要翻译： 本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置，反之亦然，特别涉及一种 单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧，具有对应于STM-j帧的聚合总容量，其中i和j是从1到64的整数或 根据SDH / SONET标准的STM-N定义更高。 此外，本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中，不存在SDH，对应于156Mb / s的STM-1的1/3的数据速率为51.5Mb / s。 根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口，用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口扫描单元 其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据，该数据流具有至少两个不同数据速率的数据流。

    Stateless message processing scheme for network processors interactions
    80.
    发明授权
    Stateless message processing scheme for network processors interactions 失效

    公开(公告)号：US07085850B2

    公开(公告)日：2006-08-01

    申请号：US09934886

    申请日：2001-08-22

    申请人： Jean Louis Calvignac ,  Mohammad Peyravian ,  Fabrice Jean Verplanken

    发明人： Jean Louis Calvignac ,  Mohammad Peyravian ,  Fabrice Jean Verplanken

    IPC分类号： G06F15/16

    CPC分类号： H04L29/06 ,  H04L69/22

    摘要： A stateless message-passing scheme for interactions between a network processor and a coprocessor is provided. The network processor, when receiving data frames for transmission from a network element to another network element encapsulates the entire packet that it receives within a frame. In this frame, there is provided a header field and a data field. The data field contains the data that needs to be transferred, and the header field contains all of the information regarding the deep-processing that the coprocessor is to perform so that no information of any type need be stored either by the network processor or separately regarding the processing of the data in the data packet. The coprocessor performs the operation designated by the header and returns the altered packet and header to the network processor.