公开(公告)号：US06380695B1

公开(公告)日：2002-04-30

申请号：US09729268

申请日：2000-12-05

申请人： Chih-Hung Lin ,  Jung Chan Hsieh

发明人： Chih-Hung Lin ,  Jung Chan Hsieh

IPC分类号： G05F100

CPC分类号： H02M7/5381 ,  H05B41/2824 ,  H05B41/3927

摘要： A driving device for a fluorescent tube has a high frequency oscillator which outputs a high frequency AC signal. A pulse width modulator is connected to the high frequency oscillator for outputting a PWM harmonic frequency signal. A first power switch is connected to the pulse width modulator for being turned off during a positive half-cycle of the PWM harmonic frequency signal and being turned on during a negative half-cycle of the PWM harmonic frequency signal. A second power switch is connected to the pulse width modulator for being turned on during the positive half-cycle of the PWM harmonic frequency signal and being turned off during the negative half-cycle of the PWM harmonic frequency signal. A piezoelectric transformer includes a primary winding having two input terminals connected to the first power switch and the second power switch, respectively, and a center terminal connected to the output terminal of the pulse width modulator.

摘要翻译： 用于荧光管的驱动装置具有输出高频AC信号的高频振荡器。 脉冲宽度调制器连接到高频振荡器，用于输出PWM谐波频率信号。 第一电源开关连接到脉宽调制器，在PWM谐波频率信号的正半周期期间被关断，并且在PWM谐波频率信号的负半周期期间导通。 第二电源开关连接到脉宽调制器，在PWM谐波频率信号的正半周期期间导通，并在PWM谐波频率信号的负半周期期间关断。 压电变压器包括分别具有连接到第一电源开关和第二电源开关的两个输入端子的初级绕组和连接到脉冲宽度调制器的输出端子的中心端子。

公开(公告)号：US06249022B1

公开(公告)日：2001-06-19

申请号：US09425395

申请日：1999-10-22

申请人： Chih-Hung Lin ,  Robin Lee

发明人： Chih-Hung Lin ,  Robin Lee

IPC分类号： H01L218228

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/7923

摘要： A method for fabricating a flash memory cell is described. A conformal ultra thin oxide layer is formed on a substrate having a trench formed therein, followed by forming silicon nitride spacers on the portion of the ultra thin oxide layer which covers the sidewalls of the trench. The silicon nitride spacers are separated into a first silicon nitride spacer on the right sidewall and a second silicon nitride spacer on the left sidewall. Thereafter, a gate oxide layer is formed on the silicon nitride spacers, followed by forming a polysilicon gate on the gate oxide layer in the substrate. Subsequently, a source/drain region is formed on both sides of the polysilicon gate in the substrate.

摘要翻译： 描述了一种制造闪存单元的方法。 在其上形成有沟槽的衬底上形成共形的超薄氧化物层，然后在覆盖沟槽的侧壁的超薄氧化物层的部分上形成氮化硅间隔物。 氮化硅间隔物被分成右侧壁上的第一氮化硅间隔物和左侧壁上的第二氮化硅间隔物。 此后，在氮化硅间隔物上形成栅极氧化层，随后在衬底的栅极氧化物层上形成多晶硅栅极。 随后，在衬底中的多晶硅栅极的两侧上形成源/漏区。

公开(公告)号：US06222237B1

公开(公告)日：2001-04-24

申请号：US09316584

申请日：1999-05-21

申请人： Chih-Hung Lin

发明人： Chih-Hung Lin

IPC分类号： H01L2362

CPC分类号： H01L27/0266 ,  H01L27/0288

摘要： A structure of an ESD protection device located between a pad and an internal circuit. The structure comprises a transistor with a source and a drain connecting to the ground, and an N+ resistor with its cross section comprising an N-well, a P-type doped region located in the N-well, and an N+ doped region located in the P-type doped region. The N+ doped region has a first terminal and a second terminal. The first terminal is connected electrically to the drain and the pad, while the second terminal is connected to the internal circuit.

摘要翻译： 位于焊盘和内部电路之间的ESD保护器件的结构。 该结构包括具有连接到地的源极和漏极的晶体管，并且N +电阻器的横截面包括N阱，位于N阱中的P型掺杂区域和位于N阱中的N +掺杂区域 P型掺杂区域。 N +掺杂区域具有第一端子和第二端子。 第一端子与漏极和焊盘电连接，而第二端子连接到内部电路。

公开(公告)号：US5726081A

公开(公告)日：1998-03-10

申请号：US544659

申请日：1995-10-18

申请人： Chih-Hung Lin ,  Gary Hong

发明人： Chih-Hung Lin ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L21/84

CPC分类号： H01L29/66772 ,  H01L29/41783 ,  H01L29/458 ,  H01L29/4908

摘要： In a method for fabricating a ULSI MOSFET with SOI structure, an additional polysilicon layer is used to form polysilicon/metal compound metal contacts on source and drain regions and a gate so as to avoid leakage current and short channel effect problems.

摘要翻译： 在制造具有SOI结构的ULSI MOSFET的方法中，使用附加多晶硅层在源极和漏极区域和栅极上形成多晶硅/金属复合金属触点，以避免漏电流和短沟道效应问题。

公开(公告)号：US5686321A

公开(公告)日：1997-11-11

申请号：US647266

申请日：1996-05-06

申请人： Joe Ko ,  Chih-Hung Lin

发明人： Joe Ko ,  Chih-Hung Lin

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66583 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/7833

摘要： The invention relates to an improved MOSFET device structure for use in ultra large scale integration and the method of forming the device structure. A local punchthrough stop region is formed directly under the gate electrode using ion implantation. The local punchthrough stop region reduces the expansion of the depletion region in the channel and thereby increases the punchthrough voltage. The local punchthrough stop region is self-aligned with the gate electrode and source/drain region so that critical spacings are maintained even for sub micron devices. The source and drain junction capacitances are also reduced. The invention can be used in either N channel or P channel MOSFET devices. The invention can be used with a conventional source/drain structure as well as a double doped drain structure and a light doped drain structure.

摘要翻译： 本发明涉及用于超大规模集成的改进的MOSFET器件结构以及形成器件结构的方法。 使用离子注入在栅电极正下方形成局部穿通停止区域。 局部穿通停止区域减小了通道中耗尽区的扩展，从而增加了穿透电压。 局部穿通停止区域与栅极电极和源极/漏极区域自对准，使得即使对于亚微米器件也保持临界间隔。 源极和漏极结电容也减小。 本发明可用于N沟道或P沟道MOSFET器件。 本发明可以与传统的源极/漏极结构以及双掺杂漏极结构和掺杂掺杂的漏极结构一起使用。

公开(公告)号：US5646056A

公开(公告)日：1997-07-08

申请号：US540776

申请日：1995-10-11

申请人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong

发明人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L21/265

CPC分类号： H01L29/456 ,  H01L29/41775 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/49

摘要： In a method for fabricating a ULSI MOSFET, an additional polysilicon layer is used to form polysilicon/metal compound metal contacts on source and drain regions and a gate so as to avoid leakage current and short channel effect problems.

摘要翻译： 在制造ULSI MOSFET的方法中，使用附加的多晶硅层在源极和漏极区域和栅极上形成多晶硅/金属复合金属触点，以避免漏电流和短沟道效应问题。

公开(公告)号：US5518941A

公开(公告)日：1996-05-21

申请号：US312122

申请日：1994-09-26

申请人： Chih-Hung Lin ,  Joe Ko

发明人： Chih-Hung Lin ,  Joe Ko

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/265

CPC分类号： H01L29/6659 ,  H01L21/76202

摘要： This invention provides a method of forming a field implant channel stop region and a device using a field implant channel stop region to improve isolation between devices in integrated circuits using field effect transistors. The field implant channel stop region is formed without the use of an extra mask or extra masking steps by means of either a large angle tilted ion implant beam or a higher energy normally directed ion implant beam. The field implant channel stop region is formed with the mask used to form the light doped drain region in place. The field implant channel stop region forms a local increase in the doping level in the device well thereby forming the channel stop region.

摘要翻译： 本发明提供一种形成场注入通道停止区域的方法和使用场注入通道停止区域的装置，以改善使用场效应晶体管的集成电路中的器件之间的隔离。 通过大角度倾斜离子注入光束或较高能量的正向定向离子注入光束，形成场注入通道停止区域，而不需要使用额外的掩模或额外的掩模步骤。 场用注入沟道阻挡区域形成有用于在适当位置形成光掺杂漏极区域的掩模。 场注入沟道停止区域在器件阱中形成掺杂水平的局部增加，从而形成沟道停止区域。

公开(公告)号：US5393693A

公开(公告)日：1995-02-28

申请号：US254533

申请日：1994-06-06

申请人： Joe Ko ,  Chih-Hung Lin

发明人： Joe Ko ,  Chih-Hung Lin

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/7621 ,  H01L21/76213

摘要： A method of forming field oxide isolation regions for submicron technology using oxygen implantation is described. A first insulating layer is formed over a silicon substrate. A second insulating layer is formed over the first insulating layer. A first opening is formed in the first and second insulating layers. Sidewall spacers are formed on the vertical surfaces of the first and second insulating layers, within the first opening, to define a second, smaller opening. A portion of the silicon substrate is removed in the region defined by the second, smaller opening, to form an etched region of the silicon substrate. The sidewall spacers are removed. Oxygen is implanted into the etched region of the silicon substrate and into the region of the silicon substrate under the former location of the sidewall spacers. A portion of the polycrystalline silicon in and above the etched region of the silicon substrate. The field oxide isolation region is formed by heating. The remainder of the first and second insulating layers are removed.

摘要翻译： 描述了使用氧气注入形成亚微米技术的场氧化物隔离区域的方法。 在硅衬底上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 在第一和第二绝缘层中形成第一开口。 在第一开口内的第一和第二绝缘层的垂直表面上形成侧壁间隔物，以限定第二较小的开口。 在由第二较小开口限定的区域中去除硅衬底的一部分，以形成硅衬底的蚀刻区域。 去除侧壁间隔物。 将氧气注入到硅衬底的蚀刻区域中并进入硅衬底的位于侧壁间隔物的前面位置的区域中。 在硅衬底的蚀刻区域内和上方的多晶硅的一部分。 通过加热形成场氧化物隔离区域。 去除第一和第二绝缘层的其余部分。

公开(公告)号：US20220028598A1

公开(公告)日：2022-01-27

申请号：US16936472

申请日：2020-07-23

申请人： Chih-Hung Lin ,  Kun-Chuan Chang

发明人： Chih-Hung Lin ,  Kun-Chuan Chang

IPC分类号： H01F27/28 ,  H01F27/24 ,  H01F27/06

摘要： A magnetic induction assembly includes a magnetic core, a primary winding, a secondary winding and a base. The primary winding is wound by a wire. The secondary winding is a conductive plate having an open loop and two contact ends. The base has a body having a through hollow. A surface of the body is formed with n partitions, where n is greater than or equal to 1. The partitions divide the body into n+1 winding areas for being selectively wound by the wire. Each of the partitions has a chamber, a through hole communicating with the through hollow and an opening allowing the secondary winding to enter the chamber. The magnetic core passes through the through hollow, the through holes and the loop of the conductive plate to magnetically couple with the primary winding and the secondary winding.

公开(公告)号：US20210090791A1

公开(公告)日：2021-03-25

申请号：US16583232

申请日：2019-09-25

申请人： Chih-Hung Lin ,  Kun-Chuan Chang

发明人： Chih-Hung Lin ,  Kun-Chuan Chang

IPC分类号： H01F27/30 ,  H01F27/32 ,  H01F27/28 ,  H01F27/29

摘要： A coil module includes a first coil set and a second coil set. The first coil set has an isolation frame. The second coil set has an open first winding body. The first winding body has two ends which are out of contact with each other. One of the two ends has a first conductive portion projecting from the first winding body. The other one of the two ends has a connecting end from which an open second winding body is integratedly outward extended. A terminal of the second winding body has a second conductive portion which is outward protrudent. The connecting end comprises a bent portion which makes the second winding body and the first winding body arranged in the same direction so that the second winding body and the first winding body are attached on two opposite sides of the isolation frame.