公开(公告)号：US06303439B1

公开(公告)日：2001-10-16

申请号：US09449297

申请日：1999-11-24

Applicant: Robin Lee ,  Chih-Hung Lin

Inventor： Robin Lee ,  Chih-Hung Lin

IPC: H01L218247

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/7887

Abstract: A method for fabricating a two-bit flash memory cell is described in which a substrate with a trench formed therein is provided. A conformal tunnel oxide layer is then formed on the substrate, followed by forming polysilicon spacers on the portion of the tunnel oxide layer which covers the sidewalls of the trench. The polysilicon spacers are separated into a first polysilicon spacer on the right sidewall and a second polysilicon spacer on the left sidewall. Thereafter, a gate oxide layer is formed on the polysilicon spacers, followed by forming a polysilicon gate on the gate oxide layer in the substrate. Subsequently, a source/drain region is formed on both sides of the polysilicon gate in the substrate.

Abstract translation: 描述了一种用于制造双位闪存单元的方法，其中提供了形成有沟槽的衬底。 然后在衬底上形成保形隧道氧化物层，随后在覆盖沟槽侧壁的隧道氧化物层的部分上形成多晶硅间隔物。 多晶硅间隔物被分离成右侧壁上的第一多晶硅间隔物和左侧壁上的第二多晶硅间隔物。 此后，在多晶硅间隔物上形成栅极氧化层，随后在衬底的栅极氧化物层上形成多晶硅栅极。 随后，在衬底中的多晶硅栅极的两侧上形成源/漏区。

公开(公告)号：US06249022B1

公开(公告)日：2001-06-19

申请号：US09425395

申请日：1999-10-22

Applicant: Chih-Hung Lin ,  Robin Lee

Inventor： Chih-Hung Lin ,  Robin Lee

IPC: H01L218228

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L29/7923

Abstract: A method for fabricating a flash memory cell is described. A conformal ultra thin oxide layer is formed on a substrate having a trench formed therein, followed by forming silicon nitride spacers on the portion of the ultra thin oxide layer which covers the sidewalls of the trench. The silicon nitride spacers are separated into a first silicon nitride spacer on the right sidewall and a second silicon nitride spacer on the left sidewall. Thereafter, a gate oxide layer is formed on the silicon nitride spacers, followed by forming a polysilicon gate on the gate oxide layer in the substrate. Subsequently, a source/drain region is formed on both sides of the polysilicon gate in the substrate.

Abstract translation: 描述了一种制造闪存单元的方法。 在其上形成有沟槽的衬底上形成共形的超薄氧化物层，然后在覆盖沟槽的侧壁的超薄氧化物层的部分上形成氮化硅间隔物。 氮化硅间隔物被分成右侧壁上的第一氮化硅间隔物和左侧壁上的第二氮化硅间隔物。 此后，在氮化硅间隔物上形成栅极氧化层，随后在衬底的栅极氧化物层上形成多晶硅栅极。 随后，在衬底中的多晶硅栅极的两侧上形成源/漏区。

公开(公告)号：USD919403S1

公开(公告)日：2021-05-18

申请号：US29715575

申请日：2019-12-03

Applicant: Chih-Hung Lin

Designer： Chih-Hung Lin

公开(公告)号：US20190023480A1

公开(公告)日：2019-01-24

申请号：US15654822

申请日：2017-07-20

Applicant: Chih-Hung Lin

Inventor： Chih-Hung Lin

IPC: B65D81/38 ,  B65D81/34 ,  B65D30/08 ,  B29C65/00

Abstract: A foldable cushion bag includes a main body and a handling unit. The main body includes a bottom wall and a sleeve wall jointed to the bottom wall. The bottom wall and the sleeve wall form a first heat sealed joint therebetween and cooperatively define a space for receiving a bottle. Each of the bottom and sleeve walls includes a multilayered structure having an outermost protecting layer, a first adhesive layer, a heat sealing layer, a second adhesive layer and an innermost cushion layer in that order. The handling unit is connected to the sleeve wall and opposite to the bottom wall. The handling unit is formed with a gripping hole.

公开(公告)号：USD722847S1

公开(公告)日：2015-02-24

申请号：US29490850

申请日：2014-05-14

Applicant: Chih-Hung Lin

Designer： Chih-Hung Lin

公开(公告)号：USD720540S1

公开(公告)日：2015-01-06

申请号：US29479816

申请日：2014-01-21

Applicant: Chih-Hung Lin

Designer： Chih-Hung Lin

公开(公告)号：US20140074472A1

公开(公告)日：2014-03-13

申请号：US13611684

申请日：2012-09-12

Applicant: Chih-Hung Lin ,  Teh-Jang Chen

Inventor： Chih-Hung Lin ,  Teh-Jang Chen

IPC: G10L15/00

CPC classification number: G10L15/00 ,  G08C17/02 ,  G08C2201/31 ,  G10L2015/223 ,  H04N21/4126 ,  H04N21/42222 ,  H04N21/43637 ,  H04N21/4394 ,  H04N2005/4428 ,  H04N2005/4432

Abstract: A voice control system is adapted for controlling an electrical appliance, and includes a host and a portable voice control device. The portable voice control device is capable of wireless communication with the host, and includes an audio pick-up unit for receiving a voice input. One of the host and the portable voice control device includes a voice recognition control module that is configured to recognize a control command from the voice input. The host controls operation of the electrical appliance according to the control command, and transmits an appliance status message to the portable voice control device. The portable voice control device further includes an output unit for outputting the appliance status message.

Abstract translation: 语音控制系统适用于控制电器，并且包括主机和便携式语音控制设备。 便携式语音控制装置能够与主机进行无线通信，并且包括用于接收语音输入的音频拾取单元。 主机和便携式语音控制装置之一包括被配置为从语音输入识别控制命令的语音识别控制模块。 主机根据控制命令控制电器的操作，并将设备状态消息发送到便携式语音控制设备。 便携式语音控制装置还包括用于输出设备状态消息的输出单元。

公开(公告)号：US08581255B2

公开(公告)日：2013-11-12

申请号：US13402883

申请日：2012-02-23

Applicant: Chuan-Sheng Wei ,  Chau-Shiang Huang ,  Wu-Liu Tsai ,  Chih-Hung Lin ,  Maw-Song Chen

Inventor： Chuan-Sheng Wei ,  Chau-Shiang Huang ,  Wu-Liu Tsai ,  Chih-Hung Lin ,  Maw-Song Chen

IPC: H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20 ,  H01L29/15

CPC classification number: H01L33/58 ,  G02F1/136213 ,  G02F1/136227 ,  H01L27/1255

Abstract: A pixel structure includes a first electrode on a substrate, a first insulation layer covering the first electrode, a gate located on the first insulation layer, a second electrode located on the first insulation layer above the first electrode, a second insulation layer covering the gate and the second electrode, a semiconductor layer located on the second insulation layer above the gate, a source and a drain that are located on the semiconductor layer, a third electrode, a third insulation layer, and a pixel electrode. The third electrode is located on the second insulation layer above the second electrode and electrically connected to the first electrode. The third insulation layer covers the source, the drain, and the third electrode. The pixel electrode is located on the third insulation layer and electrically connected to the drain.

Abstract translation: 像素结构包括基板上的第一电极，覆盖第一电极的第一绝缘层，位于第一绝缘层上的栅极，位于第一电极上方的第一绝缘层上的第二电极，覆盖栅极的第二绝缘层 并且第二电极，位于栅极上方的第二绝缘层上的半导体层，位于半导体层上的源极和漏极，第三电极，第三绝缘层和像素电极。 第三电极位于第二电极上方的第二绝缘层上并与第一电极电连接。 第三绝缘层覆盖源极，漏极和第三电极。 像素电极位于第三绝缘层上并与漏极电连接。

公开(公告)号：US08421938B2

公开(公告)日：2013-04-16

申请号：US12788301

申请日：2010-05-27

Applicant: Yi-Hui Li ,  Yu-Cheng Chen ,  Tsan-Chun Wang ,  Chih-Hung Lin ,  Tung-Huang Chen

Inventor： Yi-Hui Li ,  Yu-Cheng Chen ,  Tsan-Chun Wang ,  Chih-Hung Lin ,  Tung-Huang Chen

IPC: G02F1/136

CPC classification number: H01L27/12 ,  G02F1/136286 ,  G02F2201/40 ,  H01L27/124

Abstract: A pixel array is located on a substrate and includes a plurality of pixel sets. Each of the pixel sets includes a first scan line, a second scan line, a data line, a data signal transmission line, a first pixel unit, and a second pixel unit. The data line is not parallel to the first and the second scan lines. The data signal transmission line is disposed parallel to the first and the second scan lines and electrically connected to the data line. Distance between the first and the second scan lines is smaller than distance between the data signal transmission line and one of the first and the second scan lines. The first pixel unit is electrically connected to the first scan line and the data line. The second pixel unit is electrically connected to the second scan line and the data line.

Abstract translation: 像素阵列位于衬底上并且包括多个像素组。 每个像素组包括第一扫描线，第二扫描线，数据线，数据信号传输线，第一像素单元和第二像素单元。 数据线不平行于第一和第二扫描线。 数据信号传输线平行于第一和第二扫描线设置并与数据线电连接。 第一和第二扫描线之间的距离小于数据信号传输线与第一和第二扫描线之一之间的距离。 第一像素单元电连接到第一扫描线和数据线。 第二像素单元电连接到第二扫描线和数据线。

公开(公告)号：US20110073862A1

公开(公告)日：2011-03-31

申请号：US12712209

申请日：2010-02-25

Applicant: Yu-Cheng Chen ,  Chih-Hung Lin ,  Yi-Hui Li

Inventor： Yu-Cheng Chen ,  Chih-Hung Lin ,  Yi-Hui Li

IPC: H01L33/00 ,  H01L21/336

CPC classification number: H01L27/1288 ,  G02F1/13394 ,  G02F1/13458 ,  G02F1/1368 ,  G02F2001/136231 ,  H01L27/1214 ,  H01L27/1248

Abstract: An array structure, which includes a TFT, a passivation layer, a pixel electrode, a first connecting layer and a first spacer is provided. The TFT includes a gate, a source and a drain. The passivation layer overlays the TFT. The pixel electrode is located on the passivation layer. The first connecting layer is located on the pixel electrode and electrically connected to the pixel electrode and the drain. The first spacer is located on the first connecting layer.

Abstract translation: 提供了包括TFT，钝化层，像素电极，第一连接层和第一间隔物的阵列结构。 TFT包括栅极，源极和漏极。 钝化层覆盖TFT。 像素电极位于钝化层上。 第一连接层位于像素电极上并与像素电极和漏极电连接。 第一间隔件位于第一连接层上。