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112 条记录 (耗时 0.033 秒)

    Efficient implementation of error correction code scheme
    75.
    发明授权
    Efficient implementation of error correction code scheme 失效
    有效执行纠错码方案

    公开(公告)号：US06681340B2

    公开(公告)日：2004-01-20

    申请号：US09792533

    申请日：2001-02-23

    申请人： Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    发明人： Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    IPC分类号： G06F1110

    CPC分类号： H04L1/0043 ,  H04L1/0063

    摘要： A method and system for efficiently implementing an error correction code scheme. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. Each frame of data may be associated with a frame control block. The processor comprises a first queue configured to store one or more frame control blocks associated with one or more frames of data. The processor further comprises a second queue configured to store one or more frame control blocks not associated with a frame of data. The one or more frame control blocks associated with one or more frames of data in the first queue comprise a bit for storing a parity bit. The one or more frame control blocks in the second queue comprise a plurality of bits for storing a code of an error correction code scheme.

    摘要翻译： 一种用于有效实施纠错码方案的方法和系统。 在本发明的一个实施例中，系统包括被配置为处理数据帧的处理器。 数据帧可以与帧控制块相关联。 处理器包括被配置为存储与一个或多个数据帧相关联的一个或多个帧控制块的第一队列。 处理器还包括被配置为存储与数据帧不相关联的一个或多个帧控制块的第二队列。 与第一队列中的一个或多个数据帧相关联的一个或多个帧控制块包括用于存储奇偶校验位的位。 第二队列中的一个或多个帧控制块包括用于存储纠错码方案的代码的多个比特。

    Network processor for multiprotocol data flows
    76.
    发明授权
    Network processor for multiprotocol data flows 有权
    用于多协议数据流的网络处理器

    公开(公告)号：US06671280B1

    公开(公告)日：2003-12-30

    申请号：US09535794

    申请日：2000-03-29

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： H04L1256

    CPC分类号： H04L49/30 ,  H04L45/502 ,  H04L49/201 ,  H04L49/251 ,  H04L49/3009 ,  H04L49/602 ,  H04L49/606 ,  H04L2012/5618 ,  H04L2012/5665

    摘要： A method for integrating Asynchronous Transfer Mode (ATM) and frame-based traffic flows within a telecommunications network is disclosed. The telecommunications network includes a network processor having upside processing means for delivering an incoming flow from the telecommunications network to a switch and downside processing means for delivering outgoing network traffic from the switch to the telecommunications network. The incoming flow is initially received at the upside processing means as a frame-based flow. The incoming flow may be characterized as belonging to a group having frame-based flows and ATM flows. In response to the receipt of the incoming flow, the incoming flow is determined if it is destined for a legacy, ATM-only device. The incoming flow is then processed according to the determined routing requirements and the incoming flow characterization before delivering the incoming flow to the switch.

    摘要翻译： 公开了一种在电信网络内集成异步传输模式（ATM）和基于帧的业务流的方法。 电信网络包括具有上行处理装置的网络处理器，用于将来自电信网络的输入流传送到交换机，以及下行处理装置，用于将来自交换机的输出网络业务传送到电信网络。 最初在上行处理装置处接收输入流作为基于帧的流。 输入流可以被表征为属于具有基于帧的流和ATM流的组。 响应于接收到的流入，确定进入流是否发往传统的仅ATM设备。 然后根据确定的路由要求和输入流特性，将传入流量传送到交换机之前处理进入流。

    Queue manager for a buffer
    78.
    发明授权
    Queue manager for a buffer 失效
    队列管理器为缓冲区

    公开(公告)号：US06557053B1

    公开(公告)日：2003-04-29

    申请号：US09477179

    申请日：2000-01-04

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Michael Raymond Trombley ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Michael Raymond Trombley ,  Fabrice Jean Verplanken

    IPC分类号： G06F1314

    CPC分类号： G06F13/1673

    摘要： A bandwidth conserving queue manager for a FIFO buffer is provided, preferably on an ASIC chip and preferably including separate DRAM storage that maintains a FIFO queue which can extend beyond the data storage space of the FIFO buffer to provide additional data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multiple queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when some predetermined amount of the buffer storage space in the FIFO buffers is exceeded, data are written to and read from the additional data storage, and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a way that they are queued in a first-in, first-out (FIFO) sequence of addresses. Preferably, the data are written to and are read from the DRAM in burst mode.

    摘要翻译： 提供了用于FIFO缓冲器的带宽保存队列管理器，优选地在ASIC芯片上，并且优选地包括分离的DRAM存储器，其维持FIFO队列，其可以超出FIFO缓冲器的数据存储空间，以根据需要提供附加的数据存储空间。 在ASIC芯片上使用FIFO缓冲器来存储和检索多个队列条目。 只要队列的总大小不超过缓冲区中可用的存储空间，则不需要额外的数据存储。 然而，当超过FIFO缓冲器中的一些预定量的缓冲存储空间时，数据被写入附加数据存储器并从其中读出，并且优选地是具有用于保持数据存储设备的峰值性能的最佳尺寸的数据包，以及哪个 被写入数据存储设备，使得它们以先入先出（FIFO）地址序列排队。 优选地，以突发模式将数据写入DRAM并从DRAM读取。

    Network processor with single interface supporting tree search engine and CAM
    79.
    发明授权
    Network processor with single interface supporting tree search engine and CAM 失效
    具有单界面支持树搜索引擎和CAM的网络处理器

    公开(公告)号：US07953077B2

    公开(公告)日：2011-05-31

    申请号：US11457952

    申请日：2006-07-17

    申请人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

    发明人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

    IPC分类号： H04L12/56

    CPC分类号： H04L49/3009 ,  G11C15/00 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/90

    摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

    摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。

    SELECTIVE HEADER FIELD DISPATCH IN A NETWORK PROCESSING SYSTEM
    80.
    发明申请
    SELECTIVE HEADER FIELD DISPATCH IN A NETWORK PROCESSING SYSTEM 有权
    网络处理系统中的选择头部现场分配

    公开(公告)号：US20080253398A1

    公开(公告)日：2008-10-16

    申请号：US12144195

    申请日：2008-06-23

    申请人： Jean Louis Calvignac ,  Gordon Taylor Davis

    发明人： Jean Louis Calvignac ,  Gordon Taylor Davis

    IPC分类号： H04J3/24

    CPC分类号： H04L49/602 ,  H04L49/354 ,  H04L49/604 ,  H04L69/22

    摘要： A method and structure is disclosed for dispatching appropriate data to a network processing system comprising an improved technique for extracting protocol header fields for use by the network processor. This technique includes basic classification of a packet according to the types of protocol headers present in the packet. Based on the results of the classification, specific parameter fields are extracted from corresponding headers. All such parameter fields from one or more protocol headers in the packet are concatenated into a compressed dispatch message. Multiple of such dispatch messages are bundled into a single composite dispatch message. Thus selected header fields from N packets are passed to the network processor in a single composite dispatch message, increasing the network processor's packet forwarding capacity by a factor of N. Likewise, multiple enqueue messages are bundled into a single composite enqueue message to direct enqueue and frame alterations to be taken on the bundle of N packets.

    摘要翻译： 公开了一种用于将适当数据发送到网络处理系统的方法和结构，该网络处理系统包括用于提取网络处理器使用的协议报头字段的改进技术。 该技术包括根据分组中存在的协议报头的类型对分组的基本分类。 根据分类结果，从相应的标题中提取特定参数字段。 来自分组中的一个或多个协议报头的所有这些参数字段被连接成压缩的调度消息。 多个这样的分派消息被捆绑成单个复合调度消息。 因此，来自N个分组的所选择的报头字段以单个复合调度消息传递到网络处理器，从而将网络处理器的分组转发能力提高N倍。同样地，多个入队消息被捆绑到单个复合入口消息中以指导入队， 在N个数据包的束上进行帧改变。