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    Full match (FM) search algorithm implementation for a network processor
    71.
    发明授权
    Full match (FM) search algorithm implementation for a network processor 失效
    网络处理器的完全匹配（FM）搜索算法实现

    公开(公告)号：US07139753B2

    公开(公告)日：2006-11-21

    申请号：US10650327

    申请日：2003-08-28

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： G06F7/00 ,  H04L12/28

    CPC分类号： H04L45/742 ,  H04L45/7453 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99936 ,  Y10S707/99937 ,  Y10S707/99943 ,  Y10S707/99945

    摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.

    摘要翻译： 用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。 键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。 搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。 检索所需的两个密钥和相应的信息都存储在Patricia树结构中。 散列函数提供密钥的比特到散列密钥的比特的n> n映射。 用于存储散列键和树中相关信息的数据结构称为叶。 每个叶对应于与输入键完全匹配的单个键。 叶包含关键以及其他信息。 叶片的长度是可编程的，密钥的长度也是可编程的。 叶存储在随机存取存储器中，并被实现为单个存储器条目。 如果键位于直接表中，则称为直接叶。

    Method and apparatus for processing frame classification information between network processors
    73.
    发明授权
    Method and apparatus for processing frame classification information between network processors 失效
    用于处理网络处理器之间帧分类信息的方法和装置

    公开(公告)号：US07106730B1

    公开(公告)日：2006-09-12

    申请号：US09546833

    申请日：2000-04-11

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： H04L12/56

    CPC分类号： H04L49/30

    摘要： A network device including an ingress processor and egress processor which receives frames of data over the network on an input port, and transfers it to an appropriate output port. The received frame is processed by an ingress processor which prepares an intra-switch frame for delivery to an egress processor serving a relevant output port of the switch. The intra-switch frame includes a frame header having parameters which have been determined by the ingress processor, as well as data indicating an address for the egress processor for beginning processing of the frame. By identifying to the egress processor processing which has already taken place, the egress processor is relieved of any redundant processing of the frame. The egress processor provides a hardware frame classifier which decodes the information contained in the intra-frame header to derive parameters which have been previously computed as well as a starting address for the egress processor. By reducing the amount of redundant processing of the egress processor, total device throughput delay is reduced.

    摘要翻译： 一种网络设备，包括入口处理器和出口处理器，其在输入端口上通过网络接收数据帧，并将其传送到适当的输出端口。 接收到的帧由入口处理器处理，入口处理器准备一个内部交换帧，用于传送到服务于交换机的相关输出端口的出口处理器。 帧内切换帧包括具有由入口处理器确定的参数的帧报头，以及指示用于开始处理该帧的出口处理器的地址的数据。 通过识别已经发生的出口处理器处理，出口处理器免除了帧的任何冗余处理。 出口处理器提供硬件帧分类器，其对包含在帧内报头中的信息进行解码以导出先前已经计算的参数以及出口处理器的起始地址。 通过减少出口处理器的冗余处理量，减少了总设备吞吐量延迟。

    Stateless message processing scheme for network processors interactions
    74.
    发明授权
    Stateless message processing scheme for network processors interactions 失效

    公开(公告)号：US07085850B2

    公开(公告)日：2006-08-01

    申请号：US09934886

    申请日：2001-08-22

    申请人： Jean Louis Calvignac ,  Mohammad Peyravian ,  Fabrice Jean Verplanken

    发明人： Jean Louis Calvignac ,  Mohammad Peyravian ,  Fabrice Jean Verplanken

    IPC分类号： G06F15/16

    CPC分类号： H04L29/06 ,  H04L69/22

    摘要： A stateless message-passing scheme for interactions between a network processor and a coprocessor is provided. The network processor, when receiving data frames for transmission from a network element to another network element encapsulates the entire packet that it receives within a frame. In this frame, there is provided a header field and a data field. The data field contains the data that needs to be transferred, and the header field contains all of the information regarding the deep-processing that the coprocessor is to perform so that no information of any type need be stored either by the network processor or separately regarding the processing of the data in the data packet. The coprocessor performs the operation designated by the header and returns the altered packet and header to the network processor.

    Method and system for network processor scheduling outputs based on multiple calendars
    75.
    发明授权
    Method and system for network processor scheduling outputs based on multiple calendars 失效
    基于多个日历的网络处理器调度输出的方法和系统

    公开(公告)号：US06862292B1

    公开(公告)日：2005-03-01

    申请号：US09548910

    申请日：2000-04-13

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04L12/28

    CPC分类号： H04Q11/0478 ,  H04L47/2425 ,  H04L47/50 ,  H04L47/52 ,  H04L47/627 ,  H04L2012/5636 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L2012/5681

    摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.

    摘要翻译： 一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。 本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。 优选实施例中的优先级包括低延迟服务，最小带宽，加权公平排队以及用于在较长时间内防止用户继续超过其服务水平的系统。 本发明包括具有不同服务速率的多个日历，以允许用户选择他所期望的服务速率。 如果客户选择了高带宽的服务，客户将被包含在比客户选择较低带宽的情况下更频繁地服务的日历。

    Hybrid search memory for network processor and computer systems
    78.
    发明授权
    Hybrid search memory for network processor and computer systems 有权
    用于网络处理器和计算机系统的混合搜索存储器

    公开(公告)号：US08195705B2

    公开(公告)日：2012-06-05

    申请号：US10015165

    申请日：2001-12-11

    申请人： Jean Louis Calvignac ,  Fabrice Jean Verplanken

    发明人： Jean Louis Calvignac ,  Fabrice Jean Verplanken

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30327

    摘要： A system includes a data structure having a Direct Table (DT), Patricia-Trees, Pointers and high speed storage systems such as Contents Address Memory (CAM). The DT has a plurality of entries with each one coupled to a Patricia Tree having multiple nodes coupled to leaves. The number of Nodes, termed a threshold, that can be traversed to obtain information in the leaves is limited to a predetermined value. Once the threshold is reached a pointer indicates the address of the CAM and the address of the leaves is stored in the CAM. By using the structure and method the latency associated with tree search is significantly reduced.

    摘要翻译： 系统包括具有直接表（DT），帕特里夏树，指针和诸如内容地址存储器（CAM）的高速存储系统的数据结构。 DT具有多个条目，其中每个条目耦合到具有耦合到叶子的多个节点的Patricia Tree。 被称为阈值的节点数量，可以被遍历以获得叶子中的信息被限制到预定值。 一旦达到阈值，指针指示CAM的地址，并且叶子的地址被存储在CAM中。 通过使用结构和方法，与树搜索相关联的延迟显着降低。

    Sequence-preserving deep-packet processing in a multiprocessor system
    79.
    发明授权
    Sequence-preserving deep-packet processing in a multiprocessor system 失效
    在多处理器系统中对序列进行深度包处理

    公开(公告)号：US07327759B2

    公开(公告)日：2008-02-05

    申请号：US09912781

    申请日：2001-07-25

    申请人： Jean Louis Calvignac ,  Mohammad Peyravian ,  Fabrice Jean Verplanken

    发明人： Jean Louis Calvignac ,  Mohammad Peyravian ,  Fabrice Jean Verplanken

    IPC分类号： H04J3/24

    CPC分类号： H04L49/9094 ,  H04L47/10 ,  H04L47/34 ,  H04L49/90 ,  H04L49/9089

    摘要： Packets or frames of data may be compressed, encrypted/decrypted, filtered, classified, searched or subjected to other deep-packet processing operations before being distributed through the internet. The microprocessor system and method of the present invention provide for the orderly processing of such data packets without disrupting or changing the sequence in which the data is intended to be transmitted to its destination. This is achieved by receiving frames into an input buffer for processing. Associated with this input buffer is a unit for determining the operation to be performed on each frame. An arbitrator assigns each frame to a processing core engine. An output buffer collects the processed frames, and a sequencer forwards the processed frames from the output buffer to their destination in the same order as received by the input/output buffer. Maintaining the sequence of data transmission is particularly useful in voice transmission, such as videos and movies.

    摘要翻译： 数据包或数据帧可以在通过因特网分发之前被压缩，加密/解密，过滤，分类，搜索或经受其他深度包处理操作。 本发明的微处理器系统和方法提供这种数据分组的有序处理，而不会中断或改变数据要发送到其目的地的序列。 这通过将帧接收到用于处理的输入缓冲器中来实现。 与该输入缓冲器相关联的是用于确定要在每个帧上执行的操作的单元。 仲裁员将每个帧分配给处理核心引擎。 输出缓冲器收集经处理的帧，并且定序器按照输入/输出缓冲器接收的顺序将处理后的帧从输出缓冲区转发到其目的地。 保持数据传输的顺序在诸如视频和电影的语音传输中特别有用。