公开(公告)号：US20050071573A1

公开(公告)日：2005-03-31

申请号：US10675744

申请日：2003-09-30

申请人： John Dodson ,  James Fields ,  Guy Guthrie ,  Kenneth Wright

发明人： John Dodson ,  James Fields ,  Guy Guthrie ,  Kenneth Wright

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0835 ,  G06F12/0831 ,  G06F2212/507

摘要： A cache coherency protocol that includes a modified-invalid (Mi) state, which enables execution of a DMA Claim or DClaim operation to assign sole ownership of a cache line to a device that is going to overwrite the entire cache line without cache-to-cache data transfer. The protocol enables completion of speculatively-issued full cache line writes without requiring cache-to-cache transfer of data on the data bus during a preceding DMA Claim or DClaim operation. The modified-invalid (Mi) state assigns sole ownership of the cache line to an I/O device that has speculatively-issued a DMA Write or a processor that has speculatively-issued a DCBZ operation to overwrite the entire cache line, and the Mi state prevents data being sent to the cache line from another cache since the data will most probably be overwritten.

摘要翻译： 包括经修改的无效（Mi）状态的高速缓存一致性协议，其使得能够执行DMA声明或DClaim操作以将高速缓存行的唯一所有权分配给要覆盖整个高速缓存行的设备，而不进行高速缓存 - 缓存数据传输。 该协议允许完成推测发出的完整高速缓存行写入，而不需要在先前的DMA声明或DClaim操作期间在数据总线上缓存到高速缓存传输数据。 修改无效（Mi）状态将高速缓存行的唯一所有权分配给推测性地发出DMA写入的I / O设备或者推测发出DCBZ操作以覆盖整个高速缓存行的处理器，并且将Mi 状态可防止将数据从另一个缓存发送到高速缓存行，因为数据最有可能被覆盖。

公开(公告)号：US20060179237A1

公开(公告)日：2006-08-10

申请号：US11054173

申请日：2005-02-09

申请人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  Jeffrey Stuecheli

发明人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  Jeffrey Stuecheli

IPC分类号： G06F13/28 ,  G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0851

摘要： A method and apparatus for performing data prefetch in a multiprocessor system are disclosed. The multiprocessor system includes multiple processors, each having a cache memory. The cache memory is subdivided into multiple slices. A group of prefetch requests is initially issued by a requesting processor in the multiprocessor system. Each prefetch request is intended for one of the respective slices of the cache memory of the requesting processor. In response to the prefetch requests being missed in the cache memory of the requesting processor, the prefetch requests are merged into one combined prefetch request. The combined prefetch request is then sent to the cache memories of all the non-requesting processors within the multiprocessor system. In response to a combined clean response from the cache memories of all the non-requesting processors, data are then obtained for the combined prefetch request from a system memory.

摘要翻译： 公开了一种用于在多处理器系统中执行数据预取的方法和装置。 多处理器系统包括多个处理器，每个具有高速缓冲存储器。 缓存存储器被细分成多个片段。 一组预取请求最初由多处理器系统中的请求处理器发出。 每个预取请求用于请求处理器的高速缓冲存储器的相应片段之一。 响应于在请求处理器的高速缓冲存储器中错过的预取请求，预取请求被合并成一个组合预取请求。 然后将组合的预取请求发送到多处理器系统内的所有不请求处理器的高速缓冲存储器。 响应于来自所有非请求处理器的高速缓冲存储器的组合清洁响应，然后从系统存储器获得用于组合预取请求的数据。

公开(公告)号：US5388223A

公开(公告)日：1995-02-07

申请号：US755474

申请日：1991-09-05

申请人： Guy Guthrie ,  Jeffery L. Swarts

发明人： Guy Guthrie ,  Jeffery L. Swarts

IPC分类号： G06F13/37 ,  H04L12/433 ,  G06F13/36

CPC分类号： G06F13/37 ,  H04L12/433

摘要： A 1-bit token ring arbitration architecture where a plurality of chips which require access to a shared bus are coupled together in a ring is described. Each chip receives an arbitration in signal from the preceding member of the ring which is used to receive the token. Each chip transmits an arbitration out signal to the following member of the ring to send the token to the following member. In the preferred embodiment, the token appears as a 1 cycle active low pulse. An error signal notifies all the bus participants that a ring error has been detected. Preferably, the number of cycles the error signal is held active, the more severe the error. A request of bus (ROB) signal notifies the chip holding the token that another bus member needs to use the bus. The ROB signal allows the current holder of the token to maintain control of the bus if it has further processing on the bus as long as no other bus member needs the bus. A Token Hold Timer may be included in a ring member which defines how long the member can hold on to the token after receiving notification on the ROB line that another bus participant wants the bus.

摘要翻译： 描述了需要访问共享总线的多个芯片以环形耦合在一起的1位令牌环仲裁架构。 每个芯片从用于接收令牌的环的前一成员的信号中接收仲裁。 每个芯片向环的下一个成员发送仲裁输出信号，以将令牌发送到下一个成员。 在优选实施例中，令牌显示为1个周期的有效低电平脉冲。 错误信号通知所有总线参与者已检测到环路错误。 优选地，误差信号保持有效的周期数，误差越严重。 总线（ROB）信号的请求通知保存令牌的芯片，另一个总线成员需要使用总线。 只要没有其他总线构件需要总线，ROB信号允许令牌的当前持有者在总线上进行进一步的处理来维持总线的控制。 令牌保持定时器可以包括在环成员中，该环成员定义了在ROB线上接收到另一个总线参与者想要总线的通知之后，成员可以持续多长时间。

公开(公告)号：US20060294309A1

公开(公告)日：2006-12-28

申请号：US11168715

申请日：2005-06-28

申请人： Guy Guthrie ,  Jeffrey Kellington ,  Kevin Reick ,  Hugh Shen

发明人： Guy Guthrie ,  Jeffrey Kellington ,  Kevin Reick ,  Hugh Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0802 ,  G06F12/0897

摘要： An efficient system for bootstrap loading scans cache lines into a cache store queue during a scan phase, and then transmits the cache lines from the cache store queue to a cache memory array during a functional phase. Scan circuitry stores a given cache line in a set of latches associated with one of a plurality of cache entries in the cache store queue, and passes the cache line from the latch set to the associated cache entry. The cache lines may be scanned from test software that is external to the computer system. Read/claim dispatch logic dispatches store instructions for the cache entries to read/claim machines which write the cache lines to the cache memory array without obtaining write permission, after the read/claim machines evaluate a mode bit which indicates that cache entries in the cache store queue are scanned cache lines. In the illustrative embodiment the cache memory is an L2 cache.

摘要翻译： 引导加载的有效系统在扫描阶段将高速缓存行扫描到高速缓存存储队列中，然后在功能阶段将高速缓存行从高速缓存存储队列发送到高速缓冲存储器阵列。 扫描电路将给定的高速缓存行存储在与高速缓存存储队列中的多个高速缓存条目之一相关联的一组锁存器中，并将高速缓存线从锁存器组传递到相关联的高速缓存条目。 高速缓存行可以从计算机系统外部的测试软件扫描。 阅读/权利要求调度逻辑调度高速缓存条目的存储指令以在读取/权利要求机器评估指示高速缓存中的高速缓存条目的模式位之后读取/声明将缓存行写入高速缓冲存储器阵列而不获得写入许可的机器 存储队列被扫描缓存行。 在说明性实施例中，高速缓存存储器是L2高速缓存。