公开(公告)号：US20210116535A1

公开(公告)日：2021-04-22

申请号：US17038259

申请日：2020-09-30

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Markus Bichl ,  Dian Tresna Nugraha ,  Romain Ygnace

IPC: G01S7/292 ,  G01S7/41 ,  G01S7/40 ,  G01S7/288 ,  G01S13/50

Abstract: A method of handling radar signals of a radar system having a plurality of antennas is provided. The method may include generating a plurality of time-based radar signals based on a radar signal received by an associated antenna of the plurality of antennas, and transforming each time-based radar signal of the time-based radar signals into radar signals that each comprise a plurality of pairs of a frequency-based-value and an associated intensity value. The method includes storing the frequency-based-values and the intensity values of one frequency-based radar signal corresponding to one time-based radar signal of one antenna of the plurality of antennas; and storing each intensity value of the plurality of intensity values of another of the plurality of frequency-based radar signals based on a corresponding intensity value of the one frequency-based radar signal, wherein a stored representation of the intensity value of the other of the plurality of frequency-based radar signals has fewer bits than the corresponding stored intensity value.

公开(公告)号：US20200311863A1

公开(公告)日：2020-10-01

申请号：US16367635

申请日：2019-03-28

Applicant: Infineon Technologies AG

Inventor： Muhammad Hassan ,  Pedro Costa ,  Andre Roger ,  Romain Ygnace

IPC: G06T1/60 ,  G06T3/40 ,  G06F12/02

Abstract: A device for accessing memory configured to store an image data cube, wherein the memory has memory banks, and each memory bank has memory rows and memory columns. The device includes an input configured to receive a memory access request having a logical start address, which specifies a logical bank, a logical row, and a logical column, and a burst size; and a memory address generator configured to generate physical memory addresses based on the logical start address and the burst size, wherein any consecutive logical start addresses mapped to different memory rows are mapped to different memory banks.

公开(公告)号：US10222470B2

公开(公告)日：2019-03-05

申请号：US14931361

申请日：2015-11-03

Applicant: Infineon Technologies AG

Inventor： David Addison ,  Dian Tresna Nugraha ,  Andre Roger ,  Romain Ygnace

IPC: G01S7/35 ,  G01S13/93

Abstract: A method for processing radar signals, wherein said radar signals comprise digitized data received by at least one radar antenna, the method comprising (i) determining FFT results based on the digitized data received; and (ii) storing a first group of the FFT results, wherein the first group of FFT results comprises at least two portions, wherein a first portion of FFT results is stored with a first accuracy and a second portion of FFT results is stored with a second accuracy.

公开(公告)号：US20180356497A1

公开(公告)日：2018-12-13

申请号：US16000979

申请日：2018-06-06

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Christian Schmid ,  Romain Ygnace

IPC: G01S7/295 ,  G06F13/30 ,  G01S7/28

CPC classification number: G01S7/295 ,  G01S7/2806 ,  G06F13/30

Abstract: A device for processing radar signals is suggested, the device comprising: (i) a memory, which is arranged to store radar data and (ii) an accessor comprising a DMA engine, wherein the accessor is arranged to access data of the memory via the DMA engine, to filter the accessed data, and to forward the filtered data.

公开(公告)号：US10151826B2

公开(公告)日：2018-12-11

申请号：US15044445

申请日：2016-02-16

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Romain Ygnace

IPC: G01S13/34 ,  G01S7/288 ,  G01S7/292 ,  G01S13/93 ,  G01S7/35 ,  G01S13/524

Abstract: Techniques for radar detection based on preacquisition ramps are discussed. One example system comprises transmitter circuitry, receiver circuitry, and one or more processors. The transmitter circuitry can transmit preacquisition ramps and acquisition ramps. The receiver circuitry can receive preacquisition signals and acquisition signals based on interactions between the environment and the preacquisition ramps and acquisition ramps, respectively. The one or more processors can perform preprocessing based on the preacquisition signals to obtain interim results based on one or more of the environment or the system; generate a range Doppler map based at least in part on the acquisition signals; and evaluate the range Doppler map based at least in part on the interim results.

公开(公告)号：US09923750B2

公开(公告)日：2018-03-20

申请号：US15184114

申请日：2016-06-16

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Romain Ygnace ,  Juergen Schaefer ,  Matthias Marquardt ,  Ljudmil Anastasov

IPC: H04L27/14 ,  H04L27/16 ,  H04L27/22 ,  H04L27/26 ,  H04L27/02 ,  H04L27/10

CPC classification number: H04L27/2697 ,  H04L27/0014 ,  H04L27/02 ,  H04L27/10 ,  H04L2027/0016 ,  H04L2027/0018 ,  H04L2027/0055

Abstract: A modulator operable to control an oscillator is described. The modulator can include a memory that stores oscillator control values and a bit streaming block. The bit streaming block can generate a bit stream based on the oscillator control values and transmit the bit stream to the oscillator to control an oscillation frequency of the oscillator. The modulator can also include a bit streaming loader (BSL). The BSL can receive one or more of the oscillator control values from the memory, generate one or more corresponding bit values based on the one or more of the oscillator control values, and provide the one or more bit values to the bit streaming block. The bit streaming block can then generate the bit stream based the one or more bit values generated by the BSL.

公开(公告)号：US20140232586A1

公开(公告)日：2014-08-21

申请号：US13770260

申请日：2013-02-19

Applicant: Infineon Technologies AG

Inventor： Romain Ygnace ,  Andre Roger

IPC: G01S13/02

CPC classification number: G01S7/02 ,  G01S7/354 ,  G01S13/02 ,  G01S13/931 ,  G01S2007/2883 ,  G01S2007/356

Abstract: A device for radar applications includes a computing engine, a radar acquisition unit connected to the computing engine, a timer unit connected to the computing engine, a cascade input port, and a cascade output port. The cascade input port is configured to convey an input signal to the computing engine and the cascade output port is configured to convey an output signal from the computing engine. Further, an according system, a radar system, a vehicle with such radar system and a method are provided.

Abstract translation: 用于雷达应用的装置包括计算引擎，连接到计算引擎的雷达采集单元，连接到计算引擎的定时器单元，级联输入端口和级联输出端口。 级联输入端口被配置为将输入信号传送到计算引擎，并且级联输出端口被配置为传送来自计算引擎的输出信号。 此外，提供了一种相关系统，雷达系统，具有这种雷达系统的车辆和方法。

公开(公告)号：US20140122942A1

公开(公告)日：2014-05-01

申请号：US13662846

申请日：2012-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Antonio Vilela ,  Andre Roger

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0739 ,  G06F11/0757

Abstract: An error signal handling unit includes an error handler configured to receive an error signal indicating an error condition. The error handler is further configured to receive a recovery signal indicating a mitigation of the error condition or indicating that a mitigation of the error condition is possible. Furthermore, the error handler is further configured to output an error condition signal based on the error signal in response to a reception of the error signal if within a given delay time from the reception of the error signal, the error handler does not receive the recovery signal, and otherwise omit outputting the error condition signal.

Abstract translation: 错误信号处理单元包括错误处理器，该错误处理器被配置为接收指示错误状况的错误信号。 错误处理器还被配置为接收指示减轻错误状况的恢复信号或指示可以减轻错误状况。 此外，错误处理器还被配置为响应于错误信号的接收而输出基于误差信号的错误状态信号，如果在从接收到错误信号的给定延迟时间内，错误处理程序没有接收到恢复 信号，否则省略输出错误状态信号。