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    BRANCH PREDICTION USING MULTIPLE VERSIONS OF HISTORY DATA
    71.
    发明申请
    BRANCH PREDICTION USING MULTIPLE VERSIONS OF HISTORY DATA 有权
    使用多个版本的历史数据进行分支预测

    公开(公告)号：US20150331691A1

    公开(公告)日：2015-11-19

    申请号：US14278000

    申请日：2014-05-15

    申请人： International Business Machines Corporation

    发明人： David S. Levitan ,  Jose E. Moreira ,  Mauricio J. Serrano

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3806 ,  G06F9/30058 ,  G06F9/30149 ,  G06F9/3848 ,  G06F9/3861

    摘要： Branch prediction is provided by generating a first index from a previous instruction address and from a first branch history vector having a first length. A second index is generated from the previous instruction address and from a second branch history vector that is longer than the first vector. Using the first index, a first branch prediction is retrieved from a first branch prediction table. Using the second index, a second branch prediction is retrieved from a second branch prediction table. Based upon additional branch history data, the first branch history vector and the second branch history vector are updated. A first hash value is generated from a current instruction address and the updated first branch history vector. A second hash value is generated from the current instruction address and the updated second branch history vector. One of the branch predictions are selected based upon the hash values.

    摘要翻译： 通过从先前指令地址和具有第一长度的第一分支历史向量生成第一索引来提供分支预测。 从先前的指令地址和长于第一向量的第二分支历史向量生成第二索引。 使用第一索引，从第一分支预测表检索第一分支预测。 使用第二索引，从第二分支预测表检索第二分支预测。 基于附加的分支历史数据，更新第一分支历史矢量和第二分支历史矢量。 从当前指令地址和更新的第一分支历史向量生成第一哈希值。 从当前指令地址和更新的第二分支历史向量生成第二哈希值。 基于散列值来选择分支预测之一。

    Selective Delaying of Write Requests in Hardware Transactional Memory Systems
    72.
    发明申请
    Selective Delaying of Write Requests in Hardware Transactional Memory Systems 审中-公开
    在硬件事务内存系统中选择性延迟写请求

    公开(公告)号：US20140075121A1

    公开(公告)日：2014-03-13

    申请号：US13646011

    申请日：2012-10-05

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Colin B. Blundell ,  Harold W. Cain, III ,  Jose E. Moreira

    IPC分类号： G06F12/08

    CPC分类号： G06F9/467

    摘要： Techniques for conflict detection in hardware transactional memory (HTM) are provided. In one aspect, a method for detecting conflicts in HTM includes the following steps. Conflict detection is performed eagerly by setting read and write bits in a cache as transactions having read and write requests are made. A given one of the transactions is stalled when a conflict is detected whereby more than one of the transactions are accessing data in the cache in a conflicting way. An address of the conflicting data is placed in a predictor. The predictor is queried whenever the write requests are made to determine whether they correspond to entries in the predictor. A copy of the data corresponding to entries in the predictor is placed in a store buffer. The write bits in the cache are set and the copy of the data in the store buffer is merged in at transaction commit.

    摘要翻译： 提供了硬件事务存储器（HTM）中的冲突检测技术。 一方面，一种用于检测HTM中的冲突的方法包括以下步骤。 通过设置高速缓存中的读取和写入位来进行冲突检测，作为具有读取和写入请求的事务。 当检测到冲突时，给定的一个事务被停止，其中多于一个事务以冲突的方式访问缓存中的数据。 冲突数据的地址放在预测器中。 每当做出写入请求以确定它们是否对应于预测变量中的条目时，就会查询预测变量。 与预测器中的条目相对应的数据的副本被放置在存储缓冲器中。 设置缓存中的写入位，并在事务提交中合并存储缓冲区中的数据副本。

    Half-precision floating-point arrays at low overhead
    77.
    发明授权
    Half-precision floating-point arrays at low overhead 有权

    公开(公告)号：US11281745B2

    公开(公告)日：2022-03-22

    申请号：US16542447

    申请日：2019-08-16

    申请人： International Business Machines Corporation

    发明人： Bruce Fleischer ,  Jose E. Moreira ,  Joel A. Silberman

    IPC分类号： G06F17/16 ,  G06F7/544

    摘要： Methods and systems of matrix multiplication are described. In an example, a processor can multiply a first entry of a first vector of a first data array with a second vector of a second data array to generate a third vector of a third data array. The processor can store the third vector of the third data array in the second register file. The processor can multiply a second entry of the first vector with the second vector to generate a fourth vector of the third data array. The processor can store the fourth vector of the third data array in the second register file. The processor can combine vectors of the third data array that are stored in the second register file to produce the third data array.