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72.发明授权Modified method for forming cylinder-shaped capacitors for dynamic random access memory (DRAM) 有权用于形成用于动态随机存取存储器（DRAM）的圆柱形电容器的改进方法公开(公告)号：US06228736B1
公开(公告)日：2001-05-08
申请号：US09131117
申请日：1998-08-07
Applicant: Yu-Hua Lee , James Wu
Inventor： Yu-Hua Lee , James Wu
IPC: H01L2120
CPC classification number: H01L27/10855 , H01L28/91
Abstract: A modified method for forming cylinder-shaped stacked capacitors for DRAMs which circumvents oxide erosion due to misalignment is described. A planar silicon oxide (SiO2) first insulating layer is formed over device areas. A silicon nitride (Si3N4) etch-stop layer is deposited and first openings are etched for capacitor node contacts. A polysilicon layer is deposited and etched back to form node contacts in the first openings. A Si3N4 second etch-stop layer is deposited and etched back to form protective sidewall spacers in the first openings when the polysilicon node contact is inadvertently overetched. A second SiO2 insulating layer is deposited and second openings for bottom electrodes are etched over the node contacts. A conformal second polysilicon layer is deposited and chemically/mechanically polished back to form the bottom electrodes in the second openings. The second insulating layer is removed by wet etching to the first etch-stop layer. When the second openings are misaligned over the node contact openings, the Si3N4 sidewall spacers protect the SiO2 first insulating layer from being eroded over the devices on the substrate. The capacitors are now completed by forming an interelectrode dielectric layer on the bottom electrodes, and depositing and patterning a third polysilicon layer for top electrodes.
Abstract translation: 描述了一种用于形成用于DRAM的圆柱形叠层电容器的修改方法，其规避了由于未对准引起的氧化物侵蚀。 在器件区域上形成平面氧化硅（SiO 2）第一绝缘层。 沉积氮化硅（Si 3 N 4）蚀刻停止层，并且蚀刻用于电容器节点触点的第一开口。 沉积多晶硅层并回蚀刻以在第一开口中形成节点接触。 当多晶硅节点接触不经意地过蚀刻时，沉积并蚀刻Si 3 N 4第二蚀刻停止层以在第一开口中形成保护性侧壁间隔物。 沉积第二SiO 2绝缘层，并且在节点触点上蚀刻用于底部电极的第二开口。 沉积保形第二多晶硅层并在第二开口中化学/机械抛光以形成底部电极。 通过湿蚀刻将第二绝缘层去除到第一蚀刻停止层。 当第二开口在节点接触开口上不对准时，Si 3 N 4侧壁间隔物保护SiO 2第一绝缘层免受衬底上的器件的侵蚀。 现在通过在底部电极上形成电极间电介质层来完成电容器，并且沉积并构图用于顶部电极的第三多晶硅层。
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公开(公告)号：US6027969A
公开(公告)日：2000-02-22
申请号：US090497
申请日：1998-06-04
Applicant: Kuo Ching Huang , James Wu
Inventor： Kuo Ching Huang , James Wu
IPC: H01L21/8242 , H01L27/108
CPC classification number: H01L27/10852 , H01L27/10817
Abstract: A method for increasing the surface area, and thus the capacitance of a DRAM, stacked capacitor structure, has been developed. A storage node electrode, incorporating branches of polysilicon, is created via use of multiple polysilicon and insulator depositions, as well as via the use of dry anisotropic, and wet isotropic, etching procedures. The use of polysilicon spacers, created on the sides of silicon oxide mesas, adds a vertical component to the polysilicon branches. Removal of a portion of insulator layer from between polysilicon branches, results in exposure of the increased storage node electrode surface area. Unetched portions of the insulator layers, between polysilicon branches, supply structural support for the storage node electrode, comprised of polysilicon branches.
Abstract translation: 已经开发了用于增加DRAM层叠电容器结构的表面积以及因此增加电容的方法。 通过使用多个多晶硅和绝缘体沉积，以及通过使用干各向异性和湿各向同性的蚀刻工艺，创建了包含多晶硅分支的存储节点电极。 在硅氧化物台面的侧面产生的多晶硅间隔物的使用增加了多晶硅分支的垂直分量。 从多晶硅分支之间去除绝缘体层的一部分导致增加的存储节点电极表面积的暴露。 在多晶硅分支之间的绝缘体层的未蚀刻部分为存储节点电极提供由多晶硅分支组成的结构支撑。
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公开(公告)号：US08597379B2
公开(公告)日：2013-12-03
申请号：US13548932
申请日：2012-07-13
Applicant: Bryan L. McKinney , Steve Salamon , James Wu , Todd F. Tatar , Brian M. Schroeter , Jeffrey Phillips
Inventor： Bryan L. McKinney , Steve Salamon , James Wu , Todd F. Tatar , Brian M. Schroeter , Jeffrey Phillips
CPC classification number: H01M10/0431 , H01M2/162 , H01M2/1653 , H01M2/1673 , H01M2/1686 , H01M10/30 , Y10T29/4911 , Y10T29/49112 , Y10T29/49114
Abstract: Embodiments are described in terms of selective methods of sealing separators and jellyroll electrode assemblies and cells made using such methods. More particularly, methods of selectively heat sealing separators to encapsulate one of two electrodes for nickel-zinc rechargeable cells having jellyroll assemblies are described. Selective heat sealing may be applied to both ends of a jellyroll electrode assembly in order to selectively seal one of two electrodes on each end of the jellyroll.
Abstract translation: 根据使用这种方法制造的密封分离器和果冻电极组件和电池的选择方法来描述实施例。 更具体地，描述了选择性地热封隔板以封装具有胶冻组件的镍 - 锌可再充电电池的两个电极之一的方法。 选择性热封可以施加到果冻电极组件的两端，以便选择性地密封果冻卷的每一端上的两个电极之一。
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公开(公告)号：US08478757B2
公开(公告)日：2013-07-02
申请号：US13304565
申请日：2011-11-25
Applicant: Daniel Leibu , Jason Gamblen , James Wu , Michael Serbinis , Pamela Hilborn , Richard Penner , Tai Toh , Dan Galperin , Tony O'Donoghue
Inventor： Daniel Leibu , Jason Gamblen , James Wu , Michael Serbinis , Pamela Hilborn , Richard Penner , Tai Toh , Dan Galperin , Tony O'Donoghue
IPC: G06F7/00
CPC classification number: H04L67/306 , G06F17/30997 , G06Q30/02 , G06Q30/0269 , G09B5/00 , G09B7/00
Abstract: Methods and systems for managing profiles for electronic content. The methods and systems may involve profiles for a plurality of electronic content items. If a user interaction with an electronic content item of the plurality of electronic content items meets an event definition, the user interaction may be identified as an event associated with the electronic content and recorded in the profile.
Abstract translation: 用于管理电子内容配置文件的方法和系统。 方法和系统可以涉及用于多个电子内容项目的简档。 如果用户与多个电子内容项目中的电子内容项目的交互满足事件定义，则可以将用户交互识别为与电子内容相关联的事件并记录在简档中。
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Patent Agency Ranking
76.发明授权Method and system for packet and circuit telephony in a distributed telecommunications switching system 失效分布式电信交换系统中分组和电路电话的方法和系统公开(公告)号：US07366198B2
公开(公告)日：2008-04-29
申请号：US10384159
申请日：2003-03-07
Applicant: Tina Lee Hinch , Mann-Yi Hsieh , Chung-You Patrick Liu , Anthony Murphy Scafidi , Charles Arthur Witschorik , James Wu
Inventor： Tina Lee Hinch , Mann-Yi Hsieh , Chung-You Patrick Liu , Anthony Murphy Scafidi , Charles Arthur Witschorik , James Wu
IPC: H04L12/66
CPC classification number: H04Q3/0045 , H04L12/6402 , H04M7/1225 , H04Q2213/13034 , H04Q2213/13196 , H04Q2213/13201 , H04Q2213/13296 , H04Q2213/13389
Abstract: Methods and systems for interfacing packet and circuit telephony operations in a distributed telecommunications network. Initially, one or more digital circuit switches can be associated with the distributed telecommunications network. Thereafter, one or more network transmission elements within the distributed telecommunications network can be connected to one or more of the digital circuit switches. One or more broadband switches can then be associated with one or more of the network transmission elements, such that the broadband switches thereof interface with network transmission elements and the digital circuit switches to coordinate combined circuit and packet signaling, routing and calling processing services among varying terminals of the distributed telecommunications network.
Abstract translation: 用于在分布式电信网络中接口分组和电路电话操作的方法和系统。 最初，一个或多个数字电路交换机可以与分布式电信网络相关联。 此后，分布式电信网络内的一个或多个网络传输元件可以连接到一个或多个数字电路交换机。 一个或多个宽带交换机然后可以与一个或多个网络传输元件相关联，使得其宽带交换机与网络传输元件接口，并且数字电路切换以协调组合电路和分组信令，路由和呼叫处理服务之间的变化 分布式电信网络的终端。
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77.发明授权Method for constructing an integrated circuit device having fixed and programmable logic portions and programmable logic architecture for use therewith 有权用于构建具有固定和可编程逻辑部分的集成电路器件的方法以及与其一起使用的可编程逻辑结构公开(公告)号：US07257803B1
公开(公告)日：2007-08-14
申请号：US11224156
申请日：2005-09-12
Applicant: Steven J E Wilton , Kimberly Bozman , Noha Kafafi , James Wu
Inventor： Steven J E Wilton , Kimberly Bozman , Noha Kafafi , James Wu
IPC: G06F17/50
CPC classification number: G06F17/5054
Abstract: Integrated circuit devices having fixed and programmable logic portions are made by combining a hardware description language representation of the fixed logic and a hardware description language representation of the programmable logic to create a single hardware description language representation of a device. This allows multiple portions of programmable logic, distributed where needed in whatever size needed, to be interspersed among the fixed logic. Because the behavior of the programmable logic, rather than of the user programming, is being represented, a programmable logic architecture is provided that lacks behaviors, such as combinational loops, that would cause compilation of the hardware description language to generate errors.
Abstract translation: 具有固定和可编程逻辑部分的集成电路装置通过组合固定逻辑的硬件描述语言表示和可编程逻辑的硬件描述语言表示来创建设备的单个硬件描述语言表示。 这允许可编程逻辑的多个部分，分布在需要的任何大小的所需尺寸上，以分散在固定逻辑中。 由于可编程逻辑（而不是用户编程）的行为被表示，所以提供了一种可编程逻辑体系结构，其缺少行为，例如组合循环，这将导致硬件描述语言的编译以产生错误。
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