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71.发明授权Apparatus and method for efficiently sharing memory bandwidth in a network processor 失效在网络处理器中有效共享存储器带宽的装置和方法公开(公告)号：US06757795B2
公开(公告)日：2004-06-29
申请号：US10068392
申请日：2002-02-05
申请人： Peter I. A. Barri , Jean L. Calvignac , Marco C. Heddes , Joseph F. Logan , Alex M. M. Niemegeers , Fabrice J. Verplanken , Miroslav Vrana
发明人： Peter I. A. Barri , Jean L. Calvignac , Marco C. Heddes , Joseph F. Logan , Alex M. M. Niemegeers , Fabrice J. Verplanken , Miroslav Vrana
IPC分类号： G05F1200
CPC分类号： G06F13/18 , G06F13/161
摘要： A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.
摘要翻译： 网络处理器（NP）包括允许最大限度利用存储器的控制器。 控制器包括一个内存仲裁器，用于监视NP中请求者的内存访问请求，并授予高优先级请求者每次访问存储器所请求的所有内存带宽。 如果高优先级请求者请求的存储器带宽小于全部存储器带宽，则请求的带宽和全部存储器带宽之间的差异被分配给较低优先权请求者。 通过这样做，每个存储器访问都利用了完整的存储器带宽。
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公开(公告)号：US20080285454A1
公开(公告)日：2008-11-20
申请号：US12182118
申请日：2008-07-29
申请人： Everett A. CORL, JR. , Gordon T. Davis , Marco C. Heddes , Piyush C. Patel , Ravinder K. Sabhikhi
发明人： Everett A. CORL, JR. , Gordon T. Davis , Marco C. Heddes , Piyush C. Patel , Ravinder K. Sabhikhi
CPC分类号： G06N99/005
摘要： The present invention relates to a system for storing a plurality of multi-field classification rules in a computer system. Each multi-field classification rule includes a rule specification that itself includes a plurality of fields and a plurality of field definitions corresponding to the fields.
摘要翻译： 本发明涉及一种用于在计算机系统中存储多个多场分类规则的系统。 每个多字段分类规则包括本身包括多个字段的规则规范和对应于字段的多个字段定义。
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73.发明授权Network processor which makes thread execution control decisions based on latency event lengths 失效基于延迟事件长度的线程执行控制决策的网络处理器公开(公告)号：US07093109B1
公开(公告)日：2006-08-15
申请号：US09542189
申请日：2000-04-04
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3802
摘要： A control mechanism is established between a network processor and a tree search coprocessor to deal with latencies in accessing the data such as information formatted in a tree structure. A plurality of independent instruction execution threads are queued to enable them to have rapid access to the shared memory. If execution of a thread becomes stalled due to a latency event, full control is granted to the next thread in the queue. The grant of control is temporary when a short latency event occurs or full when a long latency event occurs. Control is returned to the original thread when a short latency event is completed. Each execution thread utilizes an instruction prefetch buffer that collects instructions for idle execution threads when the instruction bandwidth is not fully utilized by an active execution thread. The thread execution control is governed by the collective functioning of a FIFO, an arbiter and a thread control state machine.
摘要翻译： 在网络处理器和树形搜索协处理器之间建立一种控制机制来处理访问诸如以树结构格式化的信息的数据的延迟。 排队多个独立的指令执行线程使其能够快速访问共享存储器。 如果由于延迟事件导致线程执行失败，则会对队列中的下一个线程授予完全控制权。 当长时间延迟事件发生时，发生短延迟事件或满时，授权控制是暂时的。 当短暂延迟事件完成时，控制返回到原始线程。 每个执行线程使用指令预取缓冲器，当指令带宽未被活动执行线程充分利用时，该指令预取缓冲器收集空闲执行线程的指令。 线程执行控制由FIFO，仲裁器和线程控制状态机的集合功能决定。
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公开(公告)号：US06931641B1
公开(公告)日：2005-08-16
申请号：US09542206
申请日：2000-04-04
CPC分类号： G06F9/3802 , G06F9/3851
摘要： A mechanism controls a multi-thread processor so that when a fist thread encounters a latency event to a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
摘要翻译： 机构控制多线程处理器，使得当第一线程遇到延迟事件到第一预定义时间间隔时，临时控制在第一预定义时间间隔的持续时间内传送到备用执行线程，然后返回到原始线程。 当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。 第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。
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公开(公告)号：US06658584B1
公开(公告)日：2003-12-02
申请号：US09656556
申请日：2000-09-06
IPC分类号： G06F104
CPC分类号： G06F1/04
摘要： A method and structure for counting and storing the number of occurrences of each of a plurality of events occurring in a processor complex, which processor complex has at least one processor which processes multiple groups of data in a multiplicity of ways, is provided. The structure includes multiple storage devices, each of which includes a plurality of arrays of memory storage for storing count information of each event, which arrays are divided into a plurality of separately addressable groups of memory addresses in each memory array. At least one counter element is associated with each array of memory. A table is provided which contains information, including a point of reference in each array to uniquely define the structure and location of each memory array. At least one processor generates a plurality of parameters for each of the events to uniquely identify the event. A counter manager is provided which communicates with said at least one processor through its associated coprocessors and receives the parameters of each event generated from the at least one processor. The counter manager, utilizing the table and the parameters information from the at least one processor determines the unique physical address location associated with the event, reads the data from the unique address, modifies the read data according to the instructions and writes the modified data to the determined address. The invention also contemplates reading the information which has been stored for statistical evaluation at the address without modifying the stored information.
摘要翻译： 提供了一种用于计数和存储在处理器复合体中发生的多个事件中的每一个的出现次数的方法和结构，该处理器复合体具有以多种方式处理多组数据的至少一个处理器。 该结构包括多个存储设备，每个存储设备包括用于存储每个事件的计数信息的多个存储器存储阵列，哪些阵列被划分成每个存储器阵列中的多个单独可寻址的存储器地址组。 至少一个计数器元件与每个存储器阵列相关联。 提供了一个包含信息的表，其中包括每个数组中的参考点，以唯一地定义每个存储器阵列的结构和位置。 至少一个处理器为每个事件生成多个参数以唯一地识别该事件。 提供了一种计数器管理器，其经由其相关联的协处理器与所述至少一个处理器进行通信，并接收从至少一个处理器生成的每个事件的参数。 计数器管理器利用来自至少一个处理器的表和参数信息确定与事件相关联的唯一物理地址位置，从唯一地址读取数据，根据指令修改读取的数据，并将修改的数据写入 确定的地址。 本发明还考虑在不修改存储的信息的情况下读取已经存储的用于统计评估的地址的信息。
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公开(公告)号：US08006244B2
公开(公告)日：2011-08-23
申请号：US10915983
申请日：2004-08-11
IPC分类号： G06F9/46
CPC分类号： G06F9/3802 , G06F9/3851
摘要： A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
摘要翻译： 机制控制多线程处理器，使得当第一线程遇到第一预定义时间间隔的等待时间事件时，临时控制在第一预定义时间间隔的持续时间内被传送到备用执行线程，然后返回到原始线程。 当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。 第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。
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77.发明授权公开(公告)号：US06981027B1
公开(公告)日：2005-12-27
申请号：US09546653
申请日：2000-04-10
申请人： Anthony Matteo Gallo , Seeta Hariharan , Marco C. Heddes , Sridhar Rao , Colin Beaton Verrilli , Gail Irene Woodland
发明人： Anthony Matteo Gallo , Seeta Hariharan , Marco C. Heddes , Sridhar Rao , Colin Beaton Verrilli , Gail Irene Woodland
IPC分类号： G06F15/167 , G06F9/44 , G06F12/00 , G06F12/02 , G06F12/06 , G06F13/14 , H04L12/24 , H04L12/44 , H04L12/46 , H04L12/56 , H04L29/06
CPC分类号： H04L49/35 , H04L49/3009 , H04L49/90 , Y10S707/99953 , Y10S707/99956
摘要： A method and system for memory management in a network processing system provides for allocation of physical memory areas within network processors coupled to a control point processor by a bus. The allocation scheme provides a memory management layer without requiring a complete operating system interface and supports asynchronous completion of the allocation requests. Multicast allocation is supported allowing an allocation to be simultaneously requested on multiple network processors. The allocation mechanism returns a token, which may then be used to access the memory location via a protocol over the bus, and a single token may refer to an allocation made on several network processors where the actual physical addresses and memory configurations are different.
摘要翻译： 用于网络处理系统中的存储器管理的方法和系统提供通过总线分配耦合到控制点处理器的网络处理器内的物理存储器区域。 分配方案提供了一个内存管理层，而不需要完整的操作系统接口，并支持异步完成分配请求。 支持组播分配，允许在多个网络处理器上同时请求分配。 分配机制返回令牌，然后可以通过总线通过协议来访问存储器位置，并且单个令牌可以指在实际物理地址和存储器配置不同的多个网络处理器上进行的分配。
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78.发明授权System for delaying the counting of occurrences of a plurality of events occurring in a processor until the disposition of the event has been determined 失效用于延迟在处理器中发生的多个事件的发生的计数的系统，直到已经确定了事件的处理公开(公告)号：US06701447B1
公开(公告)日：2004-03-02
申请号：US09656547
申请日：2000-09-06
IPC分类号： G06F104
CPC分类号： G06F11/3466 , G06F2201/86 , G06F2201/88
摘要： A method and structure for performing a delayed counter increment is provided. The method and structure allows a counter decision to be modified based upon what the computer system hardware does with the data packet. Subsequent to the generation of a counter command, the processing of the data packet may change: for example, the data packet may be discarded instead of forwarded. Accordingly, the counter increment instruction is changed. A delayed counter increment will perform the actual counter update after the processing of the data packet is completed. In one embodiment of the invention, the counter update action is modified depending upon whether the data packet is forwarded or discarded, and a different counter is selected to be updated. This solves a problem that sometimes the forwarding code is unable to determine if some independent action may later discard a data packet.
摘要翻译： 提供了用于执行延迟计数器增量的方法和结构。 该方法和结构允许基于计算机系统硬件对数据分组进行什么来修改计数器判定。 在产生计数器命令之后，数据分组的处理可能改变：例如，数据分组可以被丢弃而不是转发。 因此，计数器递增指令被改变。 延迟计数器增量将在数据包的处理完成后执行实际的计数器更新。 在本发明的一个实施例中，根据数据分组是转发还是丢弃，并且选择不同的计数器来更新计数器更新动作。 这解决了有时转发代码无法确定某些独立操作是否可能稍后丢弃数据包的问题。
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