公开(公告)号：US06757795B2

公开(公告)日：2004-06-29

申请号：US10068392

申请日：2002-02-05

申请人： Peter I. A. Barri ,  Jean L. Calvignac ,  Marco C. Heddes ,  Joseph F. Logan ,  Alex M. M. Niemegeers ,  Fabrice J. Verplanken ,  Miroslav Vrana

发明人： Peter I. A. Barri ,  Jean L. Calvignac ,  Marco C. Heddes ,  Joseph F. Logan ,  Alex M. M. Niemegeers ,  Fabrice J. Verplanken ,  Miroslav Vrana

IPC分类号： G05F1200

CPC分类号： G06F13/18 ,  G06F13/161

摘要： A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.

摘要翻译： 网络处理器（NP）包括允许最大限度利用存储器的控制器。 控制器包括一个内存仲裁器，用于监视NP中请求者的内存访问请求，并授予高优先级请求者每次访问存储器所请求的所有内存带宽。 如果高优先级请求者请求的存储器带宽小于全部存储器带宽，则请求的带宽和全部存储器带宽之间的差异被分配给较低优先权请求者。 通过这样做，每个存储器访问都利用了完整的存储器带宽。

公开(公告)号：US06532185B2

公开(公告)日：2003-03-11

申请号：US09792605

申请日：2001-02-23

申请人： Jean Louis Calvignac ,  Peter Irma August Barri ,  Ivan Oscar Clemminck ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Bart Joseph Gerard Pauwels ,  Fabrice Jean Verplanken ,  Miroslav Vrana

发明人： Jean Louis Calvignac ,  Peter Irma August Barri ,  Ivan Oscar Clemminck ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Bart Joseph Gerard Pauwels ,  Fabrice Jean Verplanken ,  Miroslav Vrana

IPC分类号： G11C800

CPC分类号： H04L49/901 ,  G06F12/0607 ,  H04L49/90 ,  H04L49/9031

摘要： Network processors commonly utilize DRAM chips for the storage of data. Each DRAM chip contains multiple banks for quick storage of data and access to that data. Latency in the transfer or the ‘write’ of data into memory can occur because of a phenomenon referred to as memory bank polarization. By a procedure called quadword rotation, this latency effect is effectively eliminated. Data frames received by the network processor are transferred to a receive queue (FIFO). The frames are divided into segments that are written into the memory of the DRAM in accordance with a formula that rotates the distribution of each segment into the memory banks of the DRAM.

公开(公告)号：US06657962B1

公开(公告)日：2003-12-02

申请号：US09546651

申请日：2000-04-10

申请人： Peter Irma August Barri ,  Brian Mitchell Bass ,  Jean Louis Calvignac ,  Ivan Oscar Clemminck ,  Marco C. Heddes ,  Clark Debs Jeffries ,  Michael Steven Siegel ,  Fabrice Jean Verplanken ,  Miroslav Vrana

发明人： Peter Irma August Barri ,  Brian Mitchell Bass ,  Jean Louis Calvignac ,  Ivan Oscar Clemminck ,  Marco C. Heddes ,  Clark Debs Jeffries ,  Michael Steven Siegel ,  Fabrice Jean Verplanken ,  Miroslav Vrana

IPC分类号： H04L1256

CPC分类号： H04L47/2441 ,  H04L47/10 ,  H04L47/12 ,  H04L47/30 ,  H04L47/32 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/50 ,  H04L49/90

摘要： A system for minimizing congestion in a communication system is disclosed. The system comprises at least one ingress system for providing data. The ingress system includes a first free queue and a first flow queue. The system also includes a first congestion adjustment module for receiving congestion indications from the free queue and the flow queue. The first congestion adjustment module generates end stores transmit probabilities and performs per packet flow control actions. The system further includes a switch fabric for receiving data from the ingress system and for providing a congestion indication to the ingress system. The system further includes at least one egress system for receiving the data from the switch fabric. The egress system includes a second free queue and a second flow queue. The system also includes a second congestion adjustment module for receiving congestion indications from the second free queue and the second flow queue. The second congestion adjustment module generates and stores transmit probabilities and performs per packet flow control actions. Finally, the system includes a scheduler for determining the order and timing of transmission of packets out the egress system and to another node or destination. A method and system in accordance with the present invention provides for a unified method and system for logical connection of congestion with the appropriate flow control responses. The method and system utilizes congestion indicators within the ingress system, egress system, and the switch fabric in conjunction with a coarse adjustment system and fine adjustment system within the ingress device and the egress device to intelligently manage the system.

摘要翻译： 公开了一种用于最小化通信系统中的拥塞的系统。 该系统包括用于提供数据的至少一个入口系统。 入口系统包括第一空闲队列和第一流队列。 该系统还包括用于从空闲队列和流队列接收拥塞指示的第一拥塞调整模块。 第一拥塞调整模块生成终端存储发送概率并执行每个分组流控制动作。 该系统还包括用于从入口系统接收数据并向入口系统提供拥塞指示的交换结构。 该系统还包括用于从交换结构接收数据的至少一个出口系统。 出口系统包括第二空闲队列和第二流队列。 该系统还包括第二拥塞调整模块，用于从第二空闲队列和第二流队列接收拥塞指示。 第二拥塞调整模块生成并存储发送概率，并执行每个分组流控制动作。 最后，该系统包括一个调度器，用于确定出口系统和另一个节点或目的地的分组传输的顺序和定时。 根据本发明的方法和系统提供了用于将拥塞与适当流控制响应逻辑连接的统一方法和系统。 该方法和系统利用入口系统，出口系统和交换结构中的拥塞指示符与入口设备和出口设备内的粗调系统和精细调整系统结合，智能地管理系统。

公开(公告)号：US07506081B2

公开(公告)日：2009-03-17

申请号：US10850219

申请日：2004-05-20

申请人： Peter Irma August Barri ,  Jean Louis Calvignac ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken ,  Miroslav Vrana

发明人： Peter Irma August Barri ,  Jean Louis Calvignac ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken ,  Miroslav Vrana

IPC分类号： G06F3/00

CPC分类号： G11C7/1066 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093

摘要： A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory sub-system includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR DRAM or simultaneously from a plurality of the DDR DRAMs. By controlling the DDR DRAMs so that the outputs provide data serially or in parallel, the data Bandwidth is adjustable over a wide range. Similarly, data is written serially into one DDR DRAM or simultaneously into multiple DDR DRAMs. As a consequence buffers with data from the same frame are written into or read from different DDR DRAMs.

摘要翻译： 网络处理器包括胖管端口和存储器子系统，其提供足够的数据以满足胖管端口的带宽要求。 存储器子系统包括被控制的多个DDR DRAM，从而从一个DDR DRAM提取数据或者同时从多个DDR DRAM中提取数据。 通过控制DDR DRAM，使得输出串行或并行提供数据，数据带宽可在宽范围内调节。 类似地，数据被串行地写入一个DDR DRAM或同时被写入多个DDR DRAM。 因此，来自相同帧的数据的缓冲器被写入或从不同的DDR DRAM中读取。

公开(公告)号：US20080222324A1

公开(公告)日：2008-09-11

申请号：US12120419

申请日：2008-05-14

申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： G06F5/00

CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。

公开(公告)号：US07139753B2

公开(公告)日：2006-11-21

申请号：US10650327

申请日：2003-08-28

申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC分类号： G06F7/00 ,  H04L12/28

CPC分类号： H04L45/742 ,  H04L45/7453 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99936 ,  Y10S707/99937 ,  Y10S707/99943 ,  Y10S707/99945

摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.

摘要翻译： 用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。 键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。 搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。 检索所需的两个密钥和相应的信息都存储在Patricia树结构中。 散列函数提供密钥的比特到散列密钥的比特的n> n映射。 用于存储散列键和树中相关信息的数据结构称为叶。 每个叶对应于与输入键完全匹配的单个键。 叶包含关键以及其他信息。 叶片的长度是可编程的，密钥的长度也是可编程的。 叶存储在随机存取存储器中，并被实现为单个存储器条目。 如果键位于直接表中，则称为直接叶。

公开(公告)号：US07106730B1

公开(公告)日：2006-09-12

申请号：US09546833

申请日：2000-04-11

申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC分类号： H04L12/56

CPC分类号： H04L49/30

摘要： A network device including an ingress processor and egress processor which receives frames of data over the network on an input port, and transfers it to an appropriate output port. The received frame is processed by an ingress processor which prepares an intra-switch frame for delivery to an egress processor serving a relevant output port of the switch. The intra-switch frame includes a frame header having parameters which have been determined by the ingress processor, as well as data indicating an address for the egress processor for beginning processing of the frame. By identifying to the egress processor processing which has already taken place, the egress processor is relieved of any redundant processing of the frame. The egress processor provides a hardware frame classifier which decodes the information contained in the intra-frame header to derive parameters which have been previously computed as well as a starting address for the egress processor. By reducing the amount of redundant processing of the egress processor, total device throughput delay is reduced.

摘要翻译： 一种网络设备，包括入口处理器和出口处理器，其在输入端口上通过网络接收数据帧，并将其传送到适当的输出端口。 接收到的帧由入口处理器处理，入口处理器准备一个内部交换帧，用于传送到服务于交换机的相关输出端口的出口处理器。 帧内切换帧包括具有由入口处理器确定的参数的帧报头，以及指示用于开始处理该帧的出口处理器的地址的数据。 通过识别已经发生的出口处理器处理，出口处理器免除了帧的任何冗余处理。 出口处理器提供硬件帧分类器，其对包含在帧内报头中的信息进行解码以导出先前已经计算的参数以及出口处理器的起始地址。 通过减少出口处理器的冗余处理量，减少了总设备吞吐量延迟。

公开(公告)号：US06937606B2

公开(公告)日：2005-08-30

申请号：US09839010

申请日：2001-04-20

申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： H04L12/56 ,  H04L29/06

CPC分类号： H04L69/16 ,  H04L29/06 ,  H04L49/90 ,  H04L49/9094 ,  H04L69/161 ,  H04L69/166 ,  H04L69/22

摘要： Data structures, a method, and an associated transmission system for IP fragmentation and IP reassembly on network processors in order to minimize memory allocation requirements. Frame data for IP fragmentation or reassembly on a network processor is read into buffers to which are associated various control structures. The control structures permit IP fragmentation or reassembly to be accomplished without creating multiple copies of the frame or fragments.

摘要翻译： 数据结构，方法和相关的传输系统，用于网络处理器上的IP分段和IP重组，以最大限度地减少内存分配要求。 在网络处理器上进行IP分片或重组的帧数据被读入到与各种控制结构相关联的缓冲器中。 控制结构允许在不产生帧或片段的多个副本的情况下实现IP分片或重组。

公开(公告)号：US06862292B1

公开(公告)日：2005-03-01

申请号：US09548910

申请日：2000-04-13

申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04L12/28

CPC分类号： H04Q11/0478 ,  H04L47/2425 ,  H04L47/50 ,  H04L47/52 ,  H04L47/627 ,  H04L2012/5636 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L2012/5681

摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.

摘要翻译： 一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。 本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。 优选实施例中的优先级包括低延迟服务，最小带宽，加权公平排队以及用于在较长时间内防止用户继续超过其服务水平的系统。 本发明包括具有不同服务速率的多个日历，以允许用户选择他所期望的服务速率。 如果客户选择了高带宽的服务，客户将被包含在比客户选择较低带宽的情况下更频繁地服务的日历。

公开(公告)号：US06795870B1

公开(公告)日：2004-09-21

申请号：US09548907

申请日：2000-04-13

申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC分类号： G06F300

CPC分类号： H04L47/568 ,  H04L47/50

摘要： A system and method uses grouped calendars, flow queues, pointers and stored rules to process information packets so that different flow control characteristics associated with the information units are maintained.

摘要翻译： 系统和方法使用分组的日历，流队列，指针和存储的规则来处理信息分组，从而保持与信息单元相关联的不同流控制特性。