公开(公告)号：US20100262874A1

公开(公告)日：2010-10-14

申请号：US12822694

申请日：2010-06-24

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/31723 ,  G01R31/31722 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318572 ,  G06F11/261 ,  G06F11/267 ,  G06F11/27 ,  G06F11/3466

摘要： An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning circuit within the IC in response to a first clock and outputs the acquired data from the IC in response to a second clock. An addressable two pin interface loads and updates instructions and data to a TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. Trace circuitry within an IC can operate autonomously to store and output functional data occurring in the IC. The store and output operations of the trace circuitry are transparent to the functional operation of the IC. An auto-addressing RAM memory stores input data at an input address generated in response to an input clock, and outputs stored data from an output address generated in response to an output clock.

摘要翻译： 可寻址接口选择性地启用IC内的JTAG TAP域操作或跟踪域操作。 启用后，TAP从单个数据引脚接收TMS和TDI输入。 在启用之后，响应于第一时钟，跟踪域从IC内的功能电路获取数据，并且响应于第二时钟从IC输出所获取的数据。 可寻址的两针接口将指令和数据加载并更新到IC内的TAP域。 多个IC中的指令或数据更新操作同时发生。 过程使用数据帧将数据从寻址的目标设备发送到控制器，每个数据帧包括报头位和数据位。 标头位的逻辑电平用于启动，继续和停止向控制器传输数据。 控制器和多个目标设备之间的数据和时钟信号接口提供每个目标设备被单独寻址并命令执行JTAG或跟踪操作。 IC内的跟踪电路可以自主操作来存储和输出在IC中发生的功能数据。 跟踪电路的存储和输出操作对于IC的功能操作是透明的。 自动寻址RAM存储器将输入数据存储在响应于输入时钟产生的输入地址处，并且从响应于输出时钟产生的输出地址输出存储的数据。

公开(公告)号：US20100205494A1

公开(公告)日：2010-08-12

申请号：US12763781

申请日：2010-04-20

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318555 ,  G01R31/3177 ,  G01R31/318572

摘要： A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits.

摘要翻译： 在集成电路内选择替代测试电路的过程使得测试访问端口成为可能。 扫描测试指令数据被加载到测试访问端口TAP的指令寄存器中，指令数据包括用于选择备用测试电路的信息。 在加载结束时执行Update-IR指令更新操作，以从指令寄存器输出扫描测试控制信号。 锁定信号变为活动状态以禁用测试访问端口并启用扫描测试电路。

公开(公告)号：US20100199137A1

公开(公告)日：2010-08-05

申请号：US12758143

申请日：2010-04-12

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/3177 ,  G01R31/2851 ,  G01R31/318544 ,  G01R31/318547 ,  G11C29/48

摘要： A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

摘要翻译： 一种过程和装置提供一种JTAG TAP控制器（302），以使用减少的引脚数，高速DDR接口（202）来访问设备的JTAG TAP域（106）。 通过将来自TAP控制器的单独TDI和TMS信号组合成单个信号并在驱动DDR接口的TCK的上升沿和下降沿传送单个信号的TDI和TMS信号来实现接入。 TAP域可以以点对点方式或以可寻址总线方式耦合到TAP控制器。 对TAP域的访问可用于基于JTAG的设备测试，调试，编程或其他类型的基于JTAG的操作。

公开(公告)号：US07747919B2

公开(公告)日：2010-06-29

申请号：US12406348

申请日：2009-03-18

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G01R31/28

CPC分类号： G01R31/31721 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318575

摘要： A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

摘要翻译： Scan-BIST架构适用于低功耗Scan-BIST架构。 发电机102，压实机106和控制器110保持与已知技术相同。 已知的Scan-BIST架构和低功率Scan-BIST架构之间的变化包括将已知扫描路径修改为扫描路径502，以插入扫描路径A 506，B 508和C 510，并插入适配器电路 504在控制器110和扫描路径502之间的控制路径114中。

公开(公告)号：US07747918B2

公开(公告)日：2010-06-29

申请号：US12351510

申请日：2009-01-09

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G01R31/28

CPC分类号： G01R31/31723 ,  G01R31/317 ,  G01R31/31705 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/318591 ,  G01R31/318597 ,  G06F11/267

摘要： The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

摘要翻译： 本公开描述了使用JTAG Tap的TMS和/或TCK终端作为通用串行输入/输出（I / O）曼彻斯特编码通信终端。 Tap的TMS和/或TCK终端可以用作串行I / O通信通道; （1）IC和外部控制器，（2）在第一和第二IC之间，或（3）IC内的第一和第二核心电路之间。 如上所述，使用TMS和/或TCK端子作为串行I / O通道不会影响JTAG Tap的标准化操作，因为TMS和/或TCK I / O操作发生在Tap被放置在 非活跃稳态。

公开(公告)号：US20100153798A1

公开(公告)日：2010-06-17

申请号：US12712572

申请日：2010-02-25

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/31713 ,  G01R31/28 ,  G01R31/31724 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318594 ,  G06F1/12 ,  G06F13/287 ,  G06F13/4282 ,  H03K19/017509

摘要： The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

摘要翻译： 本公开描述了使用JTAG TAP的TMS和TCK终端作为通用串行输入/输出（I / O）总线的新颖方法和装置。 根据本公开，TAP的TMS终端被用作时钟信号，并且TCK终端被用作双向数据信号以允许串行通信之间发生; （1）IC和外部控制器，（2）在第一和第二IC之间，或（3）IC内的第一和第二核心电路之间。

公开(公告)号：US07739569B2

公开(公告)日：2010-06-15

申请号：US12490869

申请日：2009-06-24

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/318536

摘要： An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

摘要翻译： 集成电路或电路板包括功能电路和扫描路径。 扫描路径包括测试数据输入引线，测试数据输出引线，多路复用器和扫描单元。 专用扫描单元具有与测试数据输出分开的功能数据输出。 共享扫描单元每个都具有用于功能数据和测试数据的组合输出。 共享扫描单元串联耦合。 第一共享扫描单元的测试数据输入连接到专用扫描单元的测试数据输出。 一个共享扫描单元的组合输出耦合到另一个共享扫描单元的测试数据输入引线。 复用器具有耦合到测试数据输出的输入，连接到串联中的最后共享扫描单元的组合输出引线的输入端和连接在扫描路径中的输出。

公开(公告)号：US07720186B2

公开(公告)日：2010-05-18

申请号：US12465990

申请日：2009-05-14

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： H04L7/00

CPC分类号： G06F13/4291 ,  G01R31/31725 ,  G01R31/31726 ,  G01R31/318536 ,  G01R31/318594 ,  G06F1/04 ,  G06F1/06 ,  H04B1/18 ,  H04J3/0644 ,  H04L7/0008

摘要： Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

公开(公告)号：US20100100780A1

公开(公告)日：2010-04-22

申请号：US12640896

申请日：2009-12-17

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/31717 ,  B82Y25/00 ,  G01R31/31701 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318572 ,  G01R33/093

摘要： A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.

摘要翻译： 传播测试指令，衰减测试指令和循环测试指令提供包括JTAG边界扫描单元在内的电路之间的直流和交流互连电路的测试。 测试访问端口电路的一些补充，包括门控产生捕捉测试频闪（CTS）信号和边界扫描单元需要实施附加说明。 说明书是常规JTAG操作结构的扩展。

公开(公告)号：US07701249B2

公开(公告)日：2010-04-20

申请号：US12352139

申请日：2009-01-12

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： H03K19/173

CPC分类号： H03K19/173 ,  G01R31/31713 ,  G01R31/31715 ,  G01R31/318572

摘要： An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal. The signal path includes a switch (S), a bus holder circuit (121B), and an output buffer (19).

摘要翻译： 电子集成电路包括连接在其功能逻辑（15）和外部输出端之间的信号路径。 信号路径包括开关（S），总线保持器电路（121B）和输出缓冲器（19）。