公开(公告)号：US07529895B2

公开(公告)日：2009-05-05

申请号：US11617276

申请日：2006-12-28

申请人： Matthias A. Blumrich ,  Dong Chen ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht ,  Burkhard D. Steinmacher-Burow ,  Todd E. Takken ,  Pavlos M. Vranas

发明人： Matthias A. Blumrich ,  Dong Chen ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht ,  Burkhard D. Steinmacher-Burow ,  Todd E. Takken ,  Pavlos M. Vranas

IPC分类号： G06F13/28

CPC分类号： G06F12/0862 ,  G06F9/52 ,  G06F2212/6028

摘要： A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple perfecting for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefect rather than some other predictive algorithm. This enables hardware to effectively prefect memory access patterns that are non-contiguous, but repetitive.

摘要翻译： 与弱有序的多处理器系统相关联地提供低延迟存储器系统访问。 多处理器中的每个处理器共享资源，并且每个共享资源在锁定设备内具有关联的锁，其提供对多处理器中的多个处理器之间的同步的支持以及资源的有序共享。 当处理器拥有与该资源相关联的锁定时，处理器仅具有访问资源的权限，并且处理器拥有锁的尝试仅需要单个加载操作，而不是传统的原子负载后跟存储，使得处理器 只执行读取操作，并且硬件锁定装置执行后续的写入操作而不是处理器。 还公开了用于非连续数据结构的简单完善。 存储器线被重新定义，使得除了正常的物理存储器数据之外，每行包括足够大的指针以指向存储器中的任何其他行，其中指针用于确定哪个存储器行被提供而不是一些其它预测 算法。 这使得硬件能够有效地预处理不连续但重复的存储器访问模式。

公开(公告)号：US20090006546A1

公开(公告)日：2009-01-01

申请号：US11768784

申请日：2007-06-26

申请人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Martin Ohmacht ,  Valentina Salapura ,  Burkhard Steinmacher-Burow ,  Pavlos Vranas

发明人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Martin Ohmacht ,  Valentina Salapura ,  Burkhard Steinmacher-Burow ,  Pavlos Vranas

IPC分类号： G06F15/16

CPC分类号： G06F15/16

摘要： A method for passing remote messages in a parallel computer system formed as a network of interconnected compute nodes includes that a first compute node (A) sends a single remote message to a remote second compute node (B) in order to control the remote second compute node (B) to send at least one remote message. The method includes various steps including controlling a DMA engine at first compute node (A) to prepare the single remote message to include a first message descriptor and at least one remote message descriptor for controlling the remote second compute node (B) to send at least one remote message, including putting the first message descriptor into an injection FIFO at the first compute node (A) and sending the single remote message and the at least one remote message descriptor to the second compute node (B).

摘要翻译： 在形成为互连的计算节点的网络的并行计算机系统中传递远程消息的方法包括：第一计算节点（A）将单个远程消息发送到远程第二计算节点（B），以便控制远程第二计算 节点（B）发送至少一个远程消息。 该方法包括各种步骤，包括在第一计算节点（A）处控制DMA引擎以准备单个远程消息以包括第一消息描述符和至少一个远程消息描述符，用于控制远程第二计算节点（B）至少发送 一个远程消息，包括将第一消息描述符放在第一计算节点（A）的注入FIFO中，并将单个远程消息和至少一个远程消息描述符发送到第二计算节点（B）。

公开(公告)号：US07444385B2

公开(公告)日：2008-10-28

申请号：US10468997

申请日：2002-02-25

申请人： Matthias A. Blumrich ,  Dong Chen ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E Giampapa ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Burkhard D. Steinmacher-Burow ,  Todd E. Takken

发明人： Matthias A. Blumrich ,  Dong Chen ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E Giampapa ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Burkhard D. Steinmacher-Burow ,  Todd E. Takken

IPC分类号： G06F15/16

CPC分类号： H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338

摘要： A system and method for generating global asynchronous signals in a computing structure. Particularly, a global interrupt and barrier network is implemented that implements logic for generating global interrupt and barrier signals for controlling global asynchronous operations performed by processing elements at selected processing nodes of a computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes for communicating the global interrupt and barrier signals to the elements via low-latency paths. The global asynchronous signals respectively initiate interrupt and barrier operations at the processing nodes at times selected for optimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structure comprising a plurality of processing nodes interconnected by multiple independent networks, with each node including one or more processing elements for performing computation or communication activity as required when performing parallel algorithm operations. One multiple independent network includes a global tree network for enabling high-speed global tree communications among global tree network nodes or sub-trees thereof. The global interrupt and barrier network may operate in parallel with the global tree network for providing global asynchronous sideband signals.

摘要翻译： 一种用于在计算结构中产生全局异步信号的系统和方法。 特别地，实现了全局中断和屏障网络，其实现用于根据处理算法产生用于控制由计算结构的选定处理节点处理元件执行的全局异步操作的全局中断和屏障信号的逻辑; 并且包括用于经由低延迟路径将全局中断和屏障信号传送到元件的处理节点的物理互连。 全局异步信号分别在处理节点处启动中断和屏障操作，这些时间被选择用于优化处理算法的性能。 在一个实施例中，全局中断和屏障网络在可扩展的大规模并行超级计算设备结构中实现，该结构包括由多个独立网络互连的多个处理节点，每个节点包括用于根据需要执行计算或通信活动的一个或多个处理元件 当执行并行算法操作时。 一个多个独立网络包括全局树网络，用于在全球树网络节点或其子树之间实现高速全局树通信。 全局中断和屏障网络可以与全局树网络并行操作，以提供全局异步边带信号。

公开(公告)号：US20080263094A1

公开(公告)日：2008-10-23

申请号：US11738245

申请日：2007-04-20

申请人： Joshua Bass ,  Adam Newcomb ,  David Zimet ,  Dong Chen ,  Jonathan McKinney

发明人： Joshua Bass ,  Adam Newcomb ,  David Zimet ,  Dong Chen ,  Jonathan McKinney

IPC分类号： G06F17/30

CPC分类号： G06F16/972

摘要： Apparatus, systems, and methods disclosed herein may download one or more sets of presentation rendering property values (PRPVs) to a client processing device. Each set of PRPVs may be associated with a set of presentation characteristics of a sensory output device (SOD) used to present a multimedia presentation, a state of the SOD, or a state of a filter used to filter the presentation. A subset of PRPVs may be associated with a presentation element. A presentation page containing the presentation element may be assembled at a multi-rendered presentation server from a template, a set of controls, a view, and a dataset. The page may be assembled such that the set of PRPVs, acting upon the presentation element at the client processing device, is capable of rendering the presentation element for presentation at the SOD with a predetermined set of perceptual characteristics compatible with SOD presentation characteristics.

摘要翻译： 本文公开的装置，系统和方法可以将一组或多组呈现呈现属性值（PRPV）下载到客户端处理装置。 每组PRPV可以与用于呈现多媒体呈现，SOD的状态或用于过滤呈现的过滤器的状态的感觉输出设备（SOD）的一组呈现特征相关联。 PRPV的子集可以与表示元素相关联。 可以在多渲染呈现服务器上从模板，一组控件，视图和数据集中组合包含表示元素的呈现页面。 可以组合该页面，使得在客户端处理设备处作用于表示元素的PRPV集合能够以与SOD呈现特性兼容的预定感知特征集合在SOD上渲染呈现元素。

公开(公告)号：US20080152664A1

公开(公告)日：2008-06-26

申请号：US12002813

申请日：2007-12-19

申请人： Kenneth L. White ,  Bart C. Weimer ,  Barry Joseph Pate ,  Dong Chen

发明人： Kenneth L. White ,  Bart C. Weimer ,  Barry Joseph Pate ,  Dong Chen

IPC分类号： A61K39/00 ,  C12N5/06 ,  A61P37/00

CPC分类号： A61K39/0006 ,  G01N33/689

摘要： Identified herein are sperm ligand proteins located in the membrane of sperm, which proteins interact with the membrane of oocytes. Methods of using these proteins, or fragments or derivatives or analogs thereof, are also described. These include methods of increasing (or reducing) successful fertilization, for instance through improved sperm-oocyte binding, fusion or activation (or the blocking thereof); methods of preventing fertilization of an oocyte, for instance by inducing an immune response to at least one sperm ligand that promotes sperm-oocyte binding, sperm-oocyte fusion or oocyte activation; and methods for enhancing assisted reproductive technologies, for instance through stimulation of activation with nuclear transfer, stimulation of inactive or weak sperm, and so forth.

摘要翻译： 本文所确定的是位于精子膜中的精子配体蛋白，该蛋白质与卵母细胞膜相互作用。 还描述了使用这些蛋白质或其片段或衍生物或类似物的方法。 这些包括增加（或减少）成功受精的方法，例如通过改善的精子卵母细胞结合，融合或活化（或其阻断）; 预防卵母细胞受精的方法，例如通过诱导至少一种促进精子卵母细胞结合，精子卵母细胞融合或卵母细胞活化的精子配体的免疫应答; 以及用于增强辅助生殖技术的方法，例如通过用核转移刺激激活，刺激无活性或弱精子等。

公开(公告)号：US20080133845A1

公开(公告)日：2008-06-05

申请号：US12035085

申请日：2008-02-21

申请人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos M. Vranas

发明人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos M. Vranas

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F12/084 ,  Y02D10/13

摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each of the memory writing sources is directly connected to the dedicated input ports of all other snoop filter devices associated with all other processing units in a point-to-point interconnect fashion. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.

摘要翻译： 一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联并与之可操作地相连的一个或多个本地高速缓冲存储器。 该方法包括提供与每个处理单元相关联的窥探过滤器设备，每个窥探过滤器设备具有多个专用输入端口，用于在多处理器计算环境中从专用存储器写入源接收窥探请求。 每个存储器写入源以点对点互连方式直接连接到与所有其他处理单元相关联的所有其他窥探滤波器设备的专用输入端口。 每个窥探过滤器装置包括与多个专用输入端口相对应的多个并行操作端口窥探滤波器，该多个专用输入端口适于同时滤除从相应专用存储器写入源接收到的窥探请求，并将这些请求的子集转发到其相关联的处理单元。

公开(公告)号：US07359929B2

公开(公告)日：2008-04-15

申请号：US10706605

申请日：2003-11-12

申请人： Leung Tsang ,  Dong Chen ,  Qin Li

发明人： Leung Tsang ,  Dong Chen ,  Qin Li

IPC分类号： G06F7/38

CPC分类号： G06F17/5036 ,  G06F17/5018 ,  G06F2217/40

摘要： A technique for solving a set of wave equations in a region uses points arranged in a grid spanning the region or coefficients of wave expansion for objects located in the region. The grid points or the coefficients are partitioned into blocks on multiple levels, and block impedance matrices encoding the wave equations is derived for pairs of blocks. The block impedance matrix need not be calculated as it is written as the product of two non-square matrices, denoted U and V. Each of U and V have one linear dimension which is only of the order of the rank of the block impedance matrix levels. The rank is predetermined by coarse sampling. Two examples of the use of the invention are given: solving surface integral equations and Foldy Lax equations for partial waves.

摘要翻译： 用于求解一个区域中的一组波动方程的技术使用布置在横跨该区域的网格中的点或位于该区域中的对象的波形膨胀系数。 网格点或系数被分割成多个级别的块，并且为块对导出块编码波方程的块阻抗矩阵。 块阻抗矩阵不需要计算，因为它被写为两个非方阵矩阵的乘积，表示为U和V. U和V中的每一个具有一个线性尺寸，其仅为块阻抗矩阵的秩的级数 水平。 排名通过粗抽样预先确定。 给出了本发明使用的两个实例：求解表面积分方程和用于部分波的折叠Lax方程。

公开(公告)号：US07305487B2

公开(公告)日：2007-12-04

申请号：US10469001

申请日：2002-02-25

申请人： Matthias A. Blumrich ,  Dong Chen ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Burkhard D. Steinmacher-Burow ,  Todd E. Takken ,  Pavlos M. Vranas

发明人： Matthias A. Blumrich ,  Dong Chen ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Burkhard D. Steinmacher-Burow ,  Todd E. Takken ,  Pavlos M. Vranas

IPC分类号： G06F15/173

CPC分类号： H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338

摘要： In a massively parallel computing system having a plurality of nodes configured in m multi-dimensions, each node including a computing device, a method for routing packets towards their destination nodes is provided which includes generating at least one of a 2m plurality of compact bit vectors containing information derived from downstream nodes. A multilevel arbitration process in which downstream information stored in the compact vectors, such as link status information and fullness of downstream buffers, is used to determine a preferred direction and virtual channel for packet transmission. Preferred direction ranges are encoded and virtual channels are selected by examining the plurality of compact bit vectors. This dynamic routing method eliminates the necessity of routing tables, thus enhancing scalability of the switch.

摘要翻译： 在具有以m多维配置的多个节点的大规模并行计算系统中，每个节点包括计算设备，提供了用于向分组朝向其目的地节点路由分组的方法，其包括生成2m个多个紧凑比特向量中的至少一个 包含从下游节点导出的信息。 存储在紧凑向量中的下行信息（诸如链路状态信息和下游缓冲器的丰满度）的多级仲裁过程被用于确定分组传输的优选方向和虚拟信道。 优选的方向范围被编码，并且通过检查多个紧凑比特向量来选择虚拟信道。 这种动态路由方法消除了路由表的必要性，从而增强了交换机的可扩展性。

公开(公告)号：US07210088B2

公开(公告)日：2007-04-24

申请号：US10468996

申请日：2002-02-25

申请人： Dong Chen ,  Paul W. Coteus ,  Alan G. Gara

发明人： Dong Chen ,  Paul W. Coteus ,  Alan G. Gara

IPC分类号： G06F11/00 ,  G06F13/00 ,  G06F7/02 ,  H03M13/00

CPC分类号： H03M13/091 ,  G11B20/1833 ,  H04L1/0061

摘要： A fault isolation technique for checking the accuracy of data packets transmitted between nodes of a parallel processor. An independent crc is kept of all data sent from one processor to another, and received from one processor to another. At the end of each checkpoint, the crcs are compared. If they do not match, there was an error. The crcs may be cleared and restarted at each checkpoint. In the preferred embodiment, the basic functionality is to calculate a CRC of all packet data that has been successfully transmitted across a given link. This CRC is done on both ends of the link, thereby allowing an independent check on all data believed to have been correctly transmitted. Preferably, all links have this CRC coverage, and the CRC used in this link level check is different from that used in the packet transfer protocol. This independent check, if successfully passed, virtually eliminates the possibility that any data errors were missed during the previous transfer period.

摘要翻译： 用于检查并行处理器节点之间传输的数据包的精度的故障隔离技术。 保持从一个处理器发送到另一个处理器的所有数据的独立crc，并从一个处理器接收另一个处理器。 在每个检查点的末尾，比较crcs。 如果它们不匹配，则出现错误。 可以在每个检查点清除并重新启动crcs。 在优选实施例中，基本功能是计算已经通过给定链路成功发送的所有分组数据的CRC。 该CRC在链路的两端完成，从而允许对所有被认为已被正确发送的数据进行独立的检查。 优选地，所有链路具有该CRC覆盖，并且在该链路级检查中使用的CRC与在分组传送协议中使用的不同。 这种独立检查，如果成功通过，几乎消除了在以前的传输期间错过任何数据错误的可能性。

公开(公告)号：US07149920B2

公开(公告)日：2006-12-12

申请号：US10674952

申请日：2003-09-30

申请人： Matthew A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Burkhard D. Steinmacher-Burow ,  Pavlos M. Vranas

发明人： Matthew A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Burkhard D. Steinmacher-Burow ,  Pavlos M. Vranas

IPC分类号： G06F11/00 ,  G06F11/07

CPC分类号： G06F11/1443 ,  G06F11/0709 ,  G06F11/0793 ,  H04L1/0052 ,  H04L69/28 ,  H04L69/40 ,  H04L2001/0092

摘要： Disclosed are an error recovery method and system for use with a communication system having first and second nodes, each of said nodes having a receiver and a sender, the sender of the first node being connected to the receiver of the second node by a first cable, and the sender of the second node being connected to the receiver of the first node by a second cable. The method comprising the step of after one of the nodes detects an error, both of the nodes entering the same defined state. In particular, the receiver of the first node enters an error state, stays in the error state for a defined period of time T, and, after said defined period of time T, enters a wait state. Also, the sender of the first node sends to the receiver of the second node an error message for a defined period of time Te, and after the defined period of time Te, the sender of the first node enters an idle state.

摘要翻译： 公开了一种用于与具有第一和第二节点的通信系统一起使用的错误恢复方法和系统，每个所述节点具有接收器和发送器，第一节点的发送器通过第一电缆连接到第二节点的接收器 并且第二节点的发送者通过第二电缆连接到第一节点的接收器。 所述方法包括在所述节点中的一个检测到错误之后的两个节点进入相同的定义状态的步骤。 特别地，第一节点的接收机进入错误状态，在定义的时间段T内保持在错误状态，并且在所述定义的时间段T之后进入等待状态。 此外，第一节点的发送方在给定的时间段Te的情况下向第二节点的接收者发送错误消息，并且在定义的时间段Te之后，第一节点的发送者进入空闲状态。