公开(公告)号：US20240176745A1

公开(公告)日：2024-05-30

申请号：US18494339

申请日：2023-10-25

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F12/0871 ,  G06F12/0815

CPC classification number: G06F12/0871 ,  G06F12/0815

Abstract: A host system connected to a memory sub-system via a connection to query memory attachment capabilities of the memory sub-system in providing memory services over the connection. The memory sub-system can allocate a portion of its memory resources to provide storage services to the host system, and allocate another portion of its memory resources to provide memory services to the host system. In response to the query, the memory sub-system can provide a response containing data indicative of memory attachment capabilities of the memory sub-system. The host system can configure the memory services of the memory sub-system, such as a solid-state drive, based on the data received as a response to the query. The query and response can be implemented in the protocol over the connection for storage access, or in the protocol over the connection for memory access.

公开(公告)号：US20240176735A1

公开(公告)日：2024-05-30

申请号：US18503481

申请日：2023-11-07

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F12/02 ,  G06F12/0815

CPC classification number: G06F12/0246 ,  G06F12/0815

Abstract: A host system connected to a memory sub-system via a connection to configure memory services provided by the memory sub-system to the host system over the connection. The memory sub-system can allocate a portion of its memory resources to provide storage services to the host system, and allocate another portion of its memory resources to provide memory services to the host system. In response to a request from the host system over the connection, the memory sub-system can update configuration data of the memory services and provide the memory services according to the parameters specified by the request. The request can be implemented in the protocol over the connection for storage access, or in the protocol over the connection for memory access. The request can be implemented via a store instruction, a write command, or another command having another command identifier.

公开(公告)号：US11941254B2

公开(公告)日：2024-03-26

申请号：US17550795

申请日：2021-12-14

Applicant: Micron Technology, Inc.

Inventor： Joseph Harold Steinmetz ,  Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0673

Abstract: A memory sub-system, such as a solid state drive (SSD), having host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. During an autonomous self-test operation of the memory sub-system, the memory sub-system is configured to generate random challenges of proof of space, generate using a proof of space plot, stored in the memory cells, responses to the random challenges respectively, and determine validity of the responses to evaluate health of the memory cells.

公开(公告)号：US20240020184A1

公开(公告)日：2024-01-18

申请号：US17866357

申请日：2022-07-15

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F9/54 ,  G06F13/16

CPC classification number: G06F9/546 ,  G06F13/1668

Abstract: A storage product having a network interface and a bus switch connecting a random-access memory, a processing device, and a storage device, and connected via an external computer bus to an external processor. The storage product can receive via the network interface first messages and second messages for network storage services. The bus switch is operable to provide a first bus between the processing device and the random-access memory to buffer the first messages into the random-access memory, a second bus between the processing device and the storage device to buffer the second messages into a local memory of the storage device, and a third bus between the processor and the random-access memory to retrieve the first messages from the random-access memory and generate third messages. The storage device is configured to process the second and third messages to provide network storage services.

公开(公告)号：US20240020183A1

公开(公告)日：2024-01-18

申请号：US17866350

申请日：2022-07-15

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F9/54 ,  G06F13/16

CPC classification number: G06F9/546 ,  G06F13/1668

Abstract: A storage product having: a network interface operable on a computer network; a bus connector adapted to be connected to a computer bus; a storage device having a storage capacity accessible through network storage services provided over the network interface; and a processing device configured to at least generate storage access messages from incoming packets received by the network interface from the computer network. The storage product is operable in a standalone mode when no local host system is connected to the bus connector to control the storage product and operable in a slave mode when a local host system is connected to the bus connector to process a portion of the storage access messages.

公开(公告)号：US20240020029A1

公开(公告)日：2024-01-18

申请号：US17866355

申请日：2022-07-15

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/0607 ,  G06F3/0679

Abstract: A computing device having: a local host system running a data application; and a storage product. The storage product has: a local storage device; a network interface to receive storage access messages from a remote host system; and a processing device configured to identify, from storage access messages, a first subset for processing by the data application, and a second subset bypassing the local host system. The first subset of the storage access messages includes first write messages configured by the remote host system to write first data into the storage product. The data application running in the local host system can generate second data based at least in part on the first data. The storage product can write the second data into the local storage device in response to the first write messages.

公开(公告)号：US11861228B2

公开(公告)日：2024-01-02

申请号：US17514267

申请日：2021-10-29

Applicant: Micron Technology, Inc.

Inventor： Karl D. Schuh ,  Ali Mohammadzadeh ,  Dheeraj Srinivasan ,  Daniel J. Hubbard ,  Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0673

Abstract: Exemplary methods, apparatuses, and systems include aggregating a plurality of memory status commands Each command of the plurality of memory status commands is assigned a corresponding bit on a memory interface. The plurality of memory status commands are sent in parallel as an aggregate status command to one or more memory components via the memory interface.

公开(公告)号：US20230418494A1

公开(公告)日：2023-12-28

申请号：US17852099

申请日：2022-06-28

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory subsystem transmits a write granularity parameter that indicates a minimum memory write size of a write command to a host system. A write command is received from the host system, the write command being a size of one or more multiples of the write granularity parameter and the write command identifying one or more logical block addresses using a pointer. Data from the write command is written to a portion of non-volatile memory of the memory subsystem using a first cursor.

公开(公告)号：US11809361B1

公开(公告)日：2023-11-07

申请号：US17866349

申请日：2022-07-15

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F13/409 ,  G06F13/1668 ,  G06F13/4022

Abstract: A storage product manufactured as a computer component to facilitate network storage services. The storage product has no central processing unit. The storage product has a bus connector connectable to a computer bus. An external processor connected to the computer bus can operate as a central processing unit. The storage product has a random-access memory, a network interface, a processing device, and a storage device having a storage capacity accessible via the network interface. The bus connector provides the processor with access to the random-access memory. The processing device of the storage product can identify and separate, among messages received by the network interface, first messages for processing by the external processor and second messages for processing by the storage device.

公开(公告)号：US20230333783A1

公开(公告)日：2023-10-19

申请号：US17720136

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0689 ,  G06F3/0655 ,  G06F3/0604

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to dynamically generate Redundant Array of Independent Nodes (RAIN) parity information for zone-based memory allocations. The RAIN parity information is generated for a given zone or set of zones on the basis of whether the given zone or set of zones satisfy a zone completeness criterion. The zone completeness criterion can represent a specified size such that when a given zone reaches the specified size, the parity information for that zone is generated.