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公开(公告)号：US07073156B2
公开(公告)日：2006-07-04
申请号：US09941519
申请日：2001-08-29
CPC分类号： G06F17/5045
摘要： A circuit design parameter file is maintained for a circuit being designed by a circuit designer. This circuit design parameter file specifies a physical characteristic of the circuit. A design environment is monitored to detect the addition of a circuitry component to the circuit and a component design parameter file that specifies at least one design parameter for that added circuitry component is accessed. The circuit design parameter file is updated based on the design parameter(s) included in the component design parameter file. The circuit designer is provided with feedback concerning the physical characteristic of the circuit being designed.
摘要翻译： 为由电路设计者设计的电路维护电路设计参数文件。 该电路设计参数文件指定电路的物理特性。 监视设计环境以检测电路组件到电路的添加，并且访问指定所添加的电路组件的至少一个设计参数的组件设计参数文件。 电路设计参数文件根据组件设计参数文件中包含的设计参数进行更新。 电路设计人员提供有关正在设计的电路的物理特性的反馈。
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公开(公告)号：US06983350B1
公开(公告)日：2006-01-03
申请号：US09387109
申请日：1999-08-31
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。
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73.发明授权公开(公告)号：US06952824B1
公开(公告)日：2005-10-04
申请号：US09710439
申请日：2000-11-10
IPC分类号： G06F9/46
CPC分类号： G06F9/546 , G06F9/3851 , G06F9/3885 , G06F9/485 , G06F9/4881 , G06F9/544
摘要： A method of processing network data in a network processor includes using three or more threads to process a beginning portion, a middle portion, and an end portion of data packet. The first thread processes the beginning portion; one or more middle threads process the middle portion, and a last thread processes the end portion. First information is indirectly passed from the first thread to the last thread via a first buffer with the middle threads progressively updating the first information. Second information is directly passed from the first thread to the last thread via a second buffer.
摘要翻译： 一种在网络处理器中处理网络数据的方法包括使用三个或更多个线程来处理数据分组的开始部分，中间部分和结束部分。 第一个线程处理起始部分; 一个或多个中间线程处理中间部分，最后一个线程处理端部。 第一个信息通过第一个缓冲区从第一个线程间接传递到最后一个线程，中间线程逐渐更新第一个信息。 第二个信息通过第二个缓冲区从第一个线程直接传递到最后一个线程。
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公开(公告)号：US06792488B2
公开(公告)日：2004-09-14
申请号：US10440079
申请日：2003-05-15
IPC分类号： G06F1300
CPC分类号： G06F13/4269
摘要： A method of communicating between a first and a second processor includes the first processor sending a datum over a common control bus, and the second processor receiving the datum from the common control bus.
摘要翻译： 在第一和第二处理器之间进行通信的方法包括：第一处理器通过公共控制总线发送数据，第二处理器从公共控制总线接收数据。
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75.发明授权Employing intelligent logical models to enable concise logic representations for clarity of design description and for rapid design capture 失效采用智能逻辑模型来实现简洁的逻辑表示，以便设计描述清晰，并能快速设计公开(公告)号：US06721925B2
公开(公告)日：2004-04-13
申请号：US10025193
申请日：2001-12-18
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/5045
摘要： Representing a logic device generally includes creating a model of a logic device, where the model represents a collection of variants of the logic device. A representation of the model may be used in a logic design and a particular variant of the logic device may be selected automatically based on connections made to the representation. Connection errors may be detected automatically and a first indication may be displayed automatically when the connection errors are detected. A second indication that differs from the first indication may be displayed automatically when the connection errors are corrected.
摘要翻译： 代表逻辑设备通常包括创建逻辑设备的模型，其中模型表示逻辑设备的变体的集合。 可以在逻辑设计中使用该模型的表示，并且可以基于对表示形成的连接来自动选择逻辑设备的特定变体。 可以自动检测连接错误，并且当检测到连接错误时可以自动显示第一指示。 当修正连接错误时，可以自动显示与第一指示不同的第二指示。
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公开(公告)号：US06687246B1
公开(公告)日：2004-02-03
申请号：US09387047
申请日：1999-08-31
申请人： Gilbert Wolrich , Matthew J. Adiletta , John Cyr
发明人： Gilbert Wolrich , Matthew J. Adiletta , John Cyr
IPC分类号： H04Q1100
CPC分类号： H04L49/10 , H04L49/101 , H04L49/254 , H04L49/3045 , H04L49/45
摘要： A switch fabric includes a first plurality of data switches each having a plurality of input ports and a plurality of output ports the plurality of switches capable of switching any of its input ports to any of its output ports with the plurality of data switches having inputs coupled to a plurality of input buses so that a first byte of a first one of the input buses is coupled to a first one of the plurality of switches, and a succeeding byte of the first input bus is coupled to a succeeding one of the plurality of switches.
摘要翻译： 交换结构包括每个具有多个输入端口和多个输出端口的第一多个数据开关，所述多个开关能够将其任何输入端口切换到其任何输出端口，并且所述多个数据开关具有耦合的输入 到多个输入总线，使得输入总线中的第一个的第一字节耦合到多个开关中的第一个，并且第一输入总线的后续字节耦合到多个输入总线中的后一个 开关。
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公开(公告)号：US06631430B1
公开(公告)日：2003-10-07
申请号：US09473113
申请日：1999-12-28
IPC分类号： G06F1200
CPC分类号： G06F13/385 , Y10S370/912
摘要： Receiving bytes of data from a media device includes issuing N consecutive requests, each for M-bytes, to the media device and receiving N−1 responses of M bytes of data from the media device.
摘要翻译： 从媒体设备接收数据字节包括向媒体设备发送N个连续请求，每个M个字节用于M字节，并从媒体设备接收M字节数据的N-1个响应。
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公开(公告)号：US06625654B1
公开(公告)日：2003-09-23
申请号：US09473799
申请日：1999-12-28
IPC分类号： G06F1516
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed than even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。 该处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是指向甚至是存储体还是奇数存储器存储器排序存储器引用;以及第二存储器控制器，其基于存储器引用来优化存储器引用 被读取引用或写入引用。 还描述了用于分组处理的程序线程通信方案。
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公开(公告)号：US06587906B2
公开(公告)日：2003-07-01
申请号：US10339221
申请日：2003-01-09
IPC分类号： G06F1300
CPC分类号： G06F9/3851
摘要： A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.
摘要翻译： 描述了用于仲裁命令请求的并行多线程处理器系统和技术。 该系统包括多个微引擎，多个共享系统资源和全局命令仲裁器。 全局命令仲裁器使用基于共享系统资源和命令类型的命令请求协议来授予或拒绝共享资源的微引擎命令请求。
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80.发明授权公开(公告)号：US06532509B1
公开(公告)日：2003-03-11
申请号：US09470541
申请日：1999-12-22
IPC分类号： G06F1314
CPC分类号： G06F9/3851
摘要： A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.
摘要翻译： 描述了用于仲裁命令请求的并行多线程处理器系统和技术。 该系统包括多个微引擎，多个共享系统资源和全局命令仲裁器。 全局命令仲裁器使用基于共享系统资源和命令类型的命令请求协议来授予或拒绝共享资源的微引擎命令请求。
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