公开(公告)号：US06879928B2

公开(公告)日：2005-04-12

申请号：US10346295

申请日：2003-01-16

申请人： Joachim Gerhard Clabes ,  Lawrence Joseph Powell, Jr. ,  Daniel Lawrence Stasiak ,  Michael Fan Wang ,  Balaram Sinharoy ,  Michael Stephen Floyd

发明人： Joachim Gerhard Clabes ,  Lawrence Joseph Powell, Jr. ,  Daniel Lawrence Stasiak ,  Michael Fan Wang ,  Balaram Sinharoy ,  Michael Stephen Floyd

IPC分类号： G01R31/28 ,  G01K3/00 ,  G01K7/32 ,  G01K11/22 ,  G01K15/00 ,  G06F19/00 ,  H01L21/822 ,  H01L27/04

CPC分类号： G01K3/005 ,  G01K7/32 ,  G01K15/00

摘要： The present invention provides an integrated circuit VLSI temperature system for the calibration of threshold temperatures. A temperature sensitive ring oscillator (TSRO) generates a TSRO calibration parameter. A memory is employable to store the TSRO calibration parameter. A module is employable to determine a threshold TSRO oscillation frequency from the TSRO calibration parameter. A memory is employable for storing at least one threshold TSRO oscillation frequency.

摘要翻译： 本发明提供了用于校准阈值温度的集成电路VLSI温度系统。 温度敏感环形振荡器（TSRO）产生TSRO校准参数。 存储器可用于存储TSRO校准参数。 模块可用于从TSRO校准参数确定阈值TSRO振荡频率。 存储器可用于存储至少一个阈值TSRO振荡频率。

公开(公告)号：US06760867B2

公开(公告)日：2004-07-06

申请号：US09801611

申请日：2001-03-08

申请人： Michael Stephen Floyd ,  Balaram Sinharoy

发明人： Michael Stephen Floyd ,  Balaram Sinharoy

IPC分类号： G06F1100

CPC分类号： G06F11/261

摘要： A writeable K by P trace array with parallel inputs and outputs is incorporated within a VLSI integrated circuit. The trace array is partitioned into N sub-arrays each sub-array having M=P/N entries for the K input signals. Logic circuitry couples selected K input signals to the trace array so that M states of the K input signals may be stored in each of the N sub-arrays. A start signal enables storing of states of the K input signals at time intervals determined by a clock. The clock is counted in a counter and when M is reached the counter is reset back to an initial state. New states of the K input signals written over old states until a pre-determined event signals occurs, at which time storing the sub-array is stopped saving the stored states of the logic inputs. Writing is simultaneously started in a succeeding sub-array in the same fashion until another event signal occurs. The process continues, cyclically repeating the selection of the N sub-arrays until an error signal occurs at which time selected sub-arrays may be read out and the states of the K input signals analyzed.

摘要翻译： 具有并行输入和输出的具有P trace阵列的可写入K集成在VLSI集成电路中。 跟踪阵列被划分为N个子阵列，每个子阵列具有用于K个输入信号的M = P / N个条目。 逻辑电路将所选择的K个输入信号耦合到迹线阵列，使得K个输入信号的M个状态可被存储在每个N个子阵列中。 起始信号使得能够以由时钟确定的时间间隔存储K个输入信号的状态。 时钟在计数器中计数，当M到达时，计数器被复位回到初始状态。 直到预定事件信号发生之前写入旧状态的K个输入信号的新状态，此时存储子阵列的时间停止，从而节省逻辑输入的存储状态。 以相同的方式同时在后续的子阵列中开始写入，直到发生另一个事件信号。 该过程继续，循环重复N个子阵列的选择，直到发生错误信号，在该时间可以读出所选择的子阵列并分析K个输入信号的状态。

公开(公告)号：US06550020B1

公开(公告)日：2003-04-15

申请号：US09483260

申请日：2000-01-10

申请人： Michael Stephen Floyd ,  Kevin F. Reick ,  Timothy M. Skergan

发明人： Michael Stephen Floyd ,  Kevin F. Reick ,  Timothy M. Skergan

IPC分类号： G06F1100

CPC分类号： G06F11/2028 ,  G06F11/1417 ,  G06F11/2035

摘要： A data processing system has at least one integrated circuit containing a central processing unit (CPU) that includes at least first and second processing cores. The integrated circuit also includes input facilities that receive control input specifying which of the processing cores is to be utilized. In addition, the integrated circuit includes configuration logic that decodes the control input and, in response, selectively controls reception of input signals and transmission of output signals of one or more of the processing cores in accordance with the control input. In an illustrative embodiment, the configuration logic is partial-good logic that configures the integrated circuit to utilize the second processing core, in lieu of a defective or inactive first processing core, as a virtual first processing core.

摘要翻译： 数据处理系统具有至少一个包含至少包括第一和第二处理核心的中央处理单元（CPU）的集成电路。 该集成电路还包括接收控制输入的输入设备，该控制输入指定要使用哪个处理核心。 此外，集成电路包括对控制输入进行解码的配置逻辑，并且作为响应，根据控制输入选择性地控制输入信号的接收和一个或多个处理核的输出信号的传输。 在说明性实施例中，配置逻辑是部分良好的逻辑，其将集成电路配置为利用第二处理核，以代替有缺陷或不活动的第一处理核作为虚拟第一处理核。

公开(公告)号：US06333653B1

公开(公告)日：2001-12-25

申请号：US09435078

申请日：1999-11-04

申请人： Michael Stephen Floyd ,  Kevin F. Reick ,  Timothy Michael Skergan

发明人： Michael Stephen Floyd ,  Kevin F. Reick ,  Timothy Michael Skergan

IPC分类号： H03L700

CPC分类号： H03L7/00 ,  G06F1/06

摘要： The present invention is embodied in a clock controller for generating and controlling the phase alignment of a plurality of ratioed sub-clocks. A master clock is preferably input to a clock splitter to provide a plurality of slave clocks. Phase holds, generated from the slave clocks, are then used to gate each of the slave clocks to produce ratioed clocks that produce phase aligned clock pulses at integer factors of the master clock frequency. The clock controller controls the ratioed clocks by processing commands to start, stop, or pulse the ratioed clocks.

摘要翻译： 本发明体现在用于产生和控制多个比例子时钟的相位对准的时钟控制器中。 主时钟优选地被输入到时钟分配器以提供多个从时钟。 然后，从从时钟产生的相位保持用于门控每个从时钟以产生比率时钟，其以主时钟频率的整数因子产生相位对准的时钟脉冲。 时钟控制器通过处理启动，停止或脉冲比较时钟的命令来控制比较时钟。