公开(公告)号：US10990317B2

公开(公告)日：2021-04-27

申请号：US16553859

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Debra M. Bell ,  James S. Rehmeyer ,  Robert Bunnell ,  Nathaniel J. Meier

IPC: G06F3/06 ,  G11C17/16 ,  G11C17/18 ,  G11C11/4072 ,  G11C11/4091

Abstract: Memory devices and systems with automatic background precondition upon powerup, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells at intersections of memory rows and memory columns. The memory device further includes sense amplifiers corresponding to the memory rows. When the memory device powers on, the memory device writes one or more memory cells of the plurality of memory cells to a random data state before executing an access command received from a user, a memory controller, or a host device of the memory device. In some embodiments, to write the one or more memory cells, the memory device fires multiple memory rows at the same time without powering corresponding sense amplifiers such that data stored on memory cells of the multiple memory rows is overwritten and corrupted.

公开(公告)号：US10978132B2

公开(公告)日：2021-04-13

申请号：US16432604

申请日：2019-06-05

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Nathaniel J. Meier ,  Joo-Sang Lee

IPC: G11C11/06 ,  G11C11/406 ,  H01L25/065

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of skipped refresh operations on a memory. Memory cells of memories may need to periodically perform refresh operations. In some instances, auto-refresh operations may be periodically skipped when charge retention characteristics of the memory cells of the memory exceed the auto-refresh frequency. To reduce peak current draw during refresh operations, the skipped refresh operations may be staggered across different portions of the memory. In one example, the skipped refresh operation may be staggered in time among memory dies of the memory to limit a number of memory dies that are performing an auto-refresh operation to a maximum number. In another example, the skipped refresh operation may be staggered in time among memory banks of a single memory array to limit a number of memory banks that are performing an auto-refresh operation to a maximum number.

公开(公告)号：US10964374B2

公开(公告)日：2021-03-30

申请号：US16549411

申请日：2019-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew D. Jenkinson ,  Nathaniel J. Meier ,  Dennis G. Montierth

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic refresh allocation. Memories may be subject to row hammer attacks, where one or more wordlines are repeatedly accessed to cause data degradation in victim rows nearby to the hammered wordlines. A memory may perform background auto-refresh operations, and targeted refresh operations where victim wordlines are refreshed. The memory may monitor access patterns to the memory in order to dynamically allocate the number of targeted refresh operations and auto-refresh operations in a set of refresh operations based on if a hammer attack is occurring and the type of hammer attack which is occurring.

公开(公告)号：US20210057013A1

公开(公告)日：2021-02-25

申请号：US16549942

申请日：2019-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew D. Jenkinson ,  Jiyun Li ,  Dennis G. Montierth ,  Nathaniel J. Meier

IPC: G11C11/408 ,  G06F12/0802 ,  H03K3/03 ,  G11C8/16

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for lossy row access counting. Row addresses along a to address bus may be sampled. When the row address is sampled it may be compared to a plurality of stored addresses in a data storage unit. If the sampled address matches one of the stored addresses, a count value associated with that address may be updated in a lust direction (such as being increased). Periodically, all of the count values may also be updated in a second direction (for example, decreased).

公开(公告)号：US20210026786A1

公开(公告)日：2021-01-28

申请号：US16518654

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Nathaniel J. Meier ,  Diana C. Majerus

IPC: G06F12/14 ,  G06F13/16 ,  G06F11/07 ,  G11C16/26 ,  G11C29/52

Abstract: Methods, apparatuses and systems related to managing access to a memory device are described. A dynamic random access memory (DRAM) device may limit or restrict access. In some cases, a memory device may be operated in a secure mode following issuance of a sequence of commands or based on a certain timing (e.g., based on clock cycles or an oscillator). A mode register of the memory device may be used to enable or disable certain modes of operation, including secure modes of operation. In some examples, a memory device may operation in an idle state while in a secure mode, and it may ignore (e.g., take no action in response to) certain commands while in the idle mode. A device may ignore commands if it identifies a mismatch in clock cycles or oscillator frequency, including when moved from one system to another without prior authentication or orderly shutdown.